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| 8xc196l x supplement to 8xc196k x, 8xc196j x , 87c196ca use r s manual a u gust 2004 o r de r n u mb e r : 272 9 73 - 0 0 3
in f o r m a t i o n i n th i s do c um e n t i s p r ov i d e d i n co n n e c t i o n wi t h i n t e l p r od u cts. n o li c e n se , ex p r e s s o r i m p l i e d, by e s to p p e l or ot h e r wi s e, t o a n y i n te ll e c t u a l pr o p e r ty r i g h ts i s g r a n te d by th i s d o c u m e nt. e x cep t as p r o v i de d i n int e l s t e rm s a n d c o nd i t i o n s o f s a l e f o r s u c h p r o d u cts , i n t e l a ss u m e s no l i a b ility w h a t s o e v e r , a n d i n t e l d i scl a i m s a n y e x p r e s s o r i m p li e d w a r r a n t y , r e l a ti n g t o s a l e a n d / o r u s e o f i n t e l p r o d u cts i n c l ud i n g li ab ilit y o r w a r r a n ti e s r e l a ti ng t o fit n e ss f o r a p a r t ic u l a r p u r p o s e , m e r c h a n t a b ilit y , o r i n f r i ng e m e nt o f a n y p a te n t, c o py r i gh t or ot h e r i n te ll e ctu a l pr o p e r ty r i gh t . i n te l p r o d uct s ar e n o t i n t en d ed fo r us e i n m ed i c a l , lif e s a vi n g , o r lif e s u s t a i n i n g a pp lic a t i o n s. in t e l m a y m a k e ch a n g e s t o s p ec i f i c a t i on s a n d p r o d uct des c r i p t i o n s a t a n y t i m e , wi th o ut n o t i c e . d e s i g n e r s m u st no t r e l y o n th e a b se n c e o r c h ar a c t e r i st i cs of a n y f ea t ur e s o r i n s t ruc t i ons m a rke d " r e s erv e d " o r " u n def i n e d . " i n t e l r e s e r v e s t h e s e f o r f u t u r e de f i n iti o n a n d s h a ll h a v e no r e s p o n si b ility w h a t s o e v e r f o r c o n f lic t s o r i n c o m p a t i b iliti e s a r isi n g fr o m fut u re ch a ng e s t o th e m . t h e 8 x c 19 6 lx , 8 x c 1 9 6 k x , 8 x c 1 9 6 jx a nd 87 c 1 9 6 c a m i c r op r oc e sso r s m a y c o nt a i n d e s i g n d e fec t s o r e r ro r s k n o w n as e r ra t a w h i c h m a y c aus e t h e p r o d uct s to d e v i a t e f r o m p u b li s h ed spe c i f i c at i o ns. c u r r en t ch a r a c te r i zed er r a t a a r e a v a il a b l e o n r e qu e st . c o n t ac t y ou r l o ca l i n te l sa l e s o f f i c e or y o ur d i str i b u t o r to o b t a i n th e l a tes t s pec i f i c at i o n s a n d be f or e p l ac i n g yo u r p r o d uct o r d e r . c o p i es o f d o cu m e n t s w h i c h h a ve an or d e r i n g n u m be r a n d a r e re f e r e nc e d i n th i s doc u m e n t , or ot h e r int e l li t e r at u r e m a y b e o b tai n ed b y c a ll i n g 1 - 8 00 - 54 8 - 4 72 5 o r by visitin g in t e l s w e bsit e a t htt p ://w w w . i n tel . c o m . c o p y r i g h t ? i n t e l c o r p o r at i o n, 2004 * t h i r d - pa r ty b r a n ds a n d n a me s a r e t h e p r o p e r ty o f th e i r r e s p ect i v e o w n e r s. iii contents chapter 1 guide to this manual 1.1 manual contents ................................................................................................... 1-1 1.2 related documents .............................................................................................. 1-2 chapter 2 architectural overview 2.1 microcontroller features .............................................................................. 2-1 2.2 block diagram......................................................................................................... 2-2 2.3 internal timing........................................................................................................ 2-2 2.4 external timing ...................................................................................................... 2-5 2.5 internal peripherals ........................................................................................... 2-6 2.5.1 i/o ports ................................................................................................................ ....2-7 2.5.2 synchronous serial i/o port .....................................................................................2-7 2.5.3 event processor array ..............................................................................................2-7 2.5.4 j1850 communications controller ............................................................................2-7 2.6 design considerations........................................................................................ 2-7 chapter 3 address space 3.1 address partitions ............................................................................................... 3-1 3.2 register file ............................................................................................................ 3- 2 3.3 peripheral special-function registers ...................................................... 3-4 3.4 windowing................................................................................................................. 3 -6 chapter 4 standard and pts interrupts 4.1 interrupt sources, vectors, and priorities ............................................. 4-1 4.2 interrupt registers............................................................................................. 4-2 4.2.1 interrupt mask registers ...........................................................................................4-3 4.2.2 interrupt pending registers ......................................................................................4-4 4.2.3 peripheral transaction server registers ..................................................................4-6 chapter 5 i/o ports 5.1 i/o ports overview ................................................................................................ 5-1 5.2 internal structure for ports 1, 2, 5, and 6 (bidirectional ports) .... 5-1 5.2.1 configuring ports 1, 2, 5, and 6 (bidirectional ports) ................................................5-3 5.2.2 special bidirectional port considerations .................................................................5-4 5.3 internal structure for ports 3 and 4 (address/data bus).................. 5-5 8xc196l x supplement iv chapter 6 synchronous serial i/o port 6.1 ssio 0 clock register........................................................................................... 6-1 6.2 ssio 1 clock register........................................................................................... 6-2 chapter 7 event processor array 7.1 epa functional overview ................................................................................... 7-1 7.1.1 epa mask registers .................................................................................................7-4 7.1.2 epa pending registers ............................................................................................7-5 7.1.3 epa interrupt priority vector register .......................................................................7-6 chapter 8 j1850 communications controller 8.1 j1850 functional overview................................................................................. 8-1 8.2 j1850 controller signals and registers..................................................... 8-3 8.3 j1850 controller operation ............................................................................. 8-4 8.3.1 control state machine ..............................................................................................8-4 8.3.1.1 cyclic redundancy check generator ..................................................................8-4 8.3.1.2 bus contention .....................................................................................................8-5 8.3.1.3 bit arbitration ........................................................................................................ 8-5 8.3.1.4 error detection .....................................................................................................8-5 8.3.2 symbol synchronization and timing circuitry ...........................................................8-5 8.3.2.1 clock prescaler ....................................................................................................8-6 8.3.2.2 digital filter ......................................................................................................... .8-6 8.3.2.3 delay compensation ............................................................................................8-6 8.3.2.4 symbol encoding and decoding ..........................................................................8-6 8.3.3 bit arbitration example .............................................................................................8-7 8.4 message frames ..................................................................................................... 8-8 8.4.1 standard messaging .................................................................................................8-9 8.4.1.1 header ................................................................................................................. 8-9 8.4.1.2 crc byte .............................................................................................................8- 9 8.4.1.3 normalization bit ..................................................................................................8-9 8.4.1.4 start and end message frame symbols ............................................................8-10 8.4.2 in-frame response messaging ...............................................................................8-12 8.4.2.1 ifr messaging type 1: single byte, single responder ....................................8-12 8.4.2.2 ifr messaging type 2: single byte, multiple responders ................................8-12 8.4.2.3 ifr messaging type 3: multiple bytes, single responder ................................8-13 8.5 transmitting and receiving messages ....................................................... 8-13 8.5.1 transmitting messages ...........................................................................................8-13 8.5.2 receiving messages ...............................................................................................8-15 8.5.3 ifr messages .........................................................................................................8-16 v contents 8.6 programming the j1850 controller ............................................................ 8-16 8.6.1 programming the j1850 command (j_cmd) register ..........................................8-16 8.6.2 programming the j1850 configuration (j_cfg) register ......................................8-18 8.6.3 programming the j1850 delay compensation (j_dly) register ...........................8-19 8.6.4 programming the j1850 status (j_stat) register ................................................8-21 chapter 9 minimum hardware considerations 9.1 identifying the reset source........................................................................... 9-1 9.2 design considerations for 8xc196la, lb, and ld ....................................... 9-2 chapter 10 special operating modes 10.1 internal timing...................................................................................................... 10-1 10.2 entering and exiting once mode ................................................................... 10-2 chapter 11 programming the nonvolatile memory 11.1 signature word and programming voltage values............................. 11-1 11.2 otprom address map .......................................................................................... 11-1 11.3 slave programming circuit and address map ......................................... 11-2 11.4 serial port programming circuit and address map............................. 11-4 appendix a signal descriptions a.1 functional groupings of signals ................................................................. a-1 a.2 default conditions .............................................................................................. a-7 glossary 8xc196l x supplement vi figures figure page 2-1 8xc196l x block diagram ............................................................................................2-2 2-2 clock circuitry (87c196la, lb only) ...........................................................................2-3 2-3 internal clock phases (assumes pll is bypassed).....................................................2-4 2-4 effect of clock mode on internal clkout frequency.................................................2-5 2-5 unerasable prom 1 (usfr1) register (la, lb only) ................................................2-6 3-1 register file address map ...........................................................................................3-3 4-1 interrupt mask (int_mask) register...........................................................................4-3 4-2 interrupt mask 1 (int_mask1) register......................................................................4-4 4-3 interrupt pending (int_pend) register ......................................................................4-5 4-4 interrupt pending 1 (int_pend1) register .................................................................4-6 4-5 pts select (ptssel) register ....................................................................................4-7 4-6 pts service (ptssrv) register .................................................................................4-8 5-1 ports 1, 2, 5, and 6 internal structure (87c196la, lb only) .......................................5-3 5-2 ports 3 and 4 internal structure (87c196la, lb only) ................................................5-6 6-1 ssio 0 clock (ssio0_clk) register...........................................................................6-1 6-2 ssio 1 clock (ssio1_clk) register...........................................................................6-2 7-1 epa block diagram (87c196la, lb only)...................................................................7-2 7-2 epa block diagram (83c196ld only) .........................................................................7-3 7-3 epa interrupt mask (epa_mask) register .................................................................7-4 7-4 epa interrupt mask 1 (epa_mask1) register ............................................................7-4 7-5 epa interrupt pending (epa_pend) register.............................................................7-5 7-6 epa interrupt pending 1 (epa_pend1) register........................................................7-5 7-7 epa interrupt priority vector register (epaipv)..........................................................7-6 8-1 integrated j1850 communications protocol solution...................................................8-1 8-2 j1850 communications controller block diagram .......................................................8-2 8-3 huntzicker symbol definition for j1850........................................................................8-7 8-4 typical vpw waveform................................................................................................8-7 8-5 bit arbitration example .................................................................................................8-8 8-6 j1850 message frames...............................................................................................8-9 8-7 huntzicker symbol definition for the normalization bit ..............................................8-10 8-8 definition for start and end of frame symbols ..........................................................8-11 8-9 ifr type 1 message frame.......................................................................................8-12 8-10 ifr type 2 message frame.......................................................................................8-13 8-11 ifr type 3 message frame.......................................................................................8-13 8-13 j1850 transmit message structure............................................................................8-14 8-12 j1850 transmitter (j_tx) register ............................................................................8-14 8-15 j1850 receive message structure.............................................................................8-15 8-14 j1850 receiver (j_rx) register ................................................................................8-15 8-16 j1850 command (j_cmd) register ..........................................................................8-17 8-17 j1850 configuration (j_cfg) register ......................................................................8-18 8-18 j1850 delay (j_dly) register ...................................................................................8-20 8-19 j1850 status (j_stat) register................................................................................8-21 9-1 reset source (rstsrc) register ...............................................................................9-1 10-1 clock circuitry (87c196la, lb only) .........................................................................10-2 vii contents figures figure page 11-1 slave programming circuit.........................................................................................11-3 11-2 serial port programming circuit .................................................................................11-4 a-1 87c196la 52-pin plcc package ............................................................................... a-3 a-2 87c196lb 52-pin plcc package ............................................................................... a-5 a-3 83c196ld 52-pin plcc package............................................................................... a-7 8xc196l x supplement viii tables table page 1-1 related documents ......................................................................................................1-2 2-1 features of the 8xc196l x and 8xc196k x product famiies .......................................2-1 2-2 state times at various frequencies ............................................................................2-4 2-3 relationships between input frequency, clock multiplier, and state times ...............2-5 2-4 uprom programming values and locations ..............................................................2-6 3-1 address map ................................................................................................................3 -1 3-2 register file memory addresses .................................................................................3-3 3-3 8xc196l x peripheral sfrs .........................................................................................3-4 3-4 windows ..................................................................................................................... ..3-6 4-1 interrupt sources, vectors, and priorities.....................................................................4-2 5-1 microcontroller ports.....................................................................................................5- 1 7-1 epa channels ..............................................................................................................7- 1 7-2 epa interrupt priority vectors.......................................................................................7-6 8-1 j1850 controller signals ..............................................................................................8-3 8-2 control and status registers .......................................................................................8-3 8-3 relationships between input frequency, pll, and prescaler bits ..............................8-6 8-4 huntzicker symbol timing characteristics .................................................................8-11 11-1 signature word and programming voltage values....................................................11-1 11-2 87c196la, lb otprom address map .....................................................................11-2 11-3 slave programming mode address map....................................................................11-3 11-4 serial port programming mode address map ............................................................11-5 a-1 87c196la signals arranged by functional categories .............................................. a-2 a-2 87c196lb signals arranged by functional categories .............................................. a-4 a-3 83c196ld signals arranged by functional categories .............................................. a-6 a-4 definition of status symbols ....................................................................................... a-7 a-5 87c196la, lb default signal conditions.................................................................... a-8 a-6 83c196ld default signal conditions .......................................................................... a-9 1 guide to this manual 1-1 chapter 1 guide to this manual this document is a supplement to the 8xc196kx, 8xc196jx, 87c196ca microcontroller family users manual . it describes the differences between the 8xc196l x and the 8xc196k x family of microcontrollers. for information not found in this supplement, please consult the 8xc196kx, 8xc196jx, 87c196ca microcontroller family users manual (order number 272258) or the 8xc196l x datasheets listed in the related documents section of this chapter. 1.1 manual contents this supplement contains several chapters, an appendix, a glossary, and an index. this chapter, chapter 1, provides an overview of the supplement. this section summarizes the contents of the remaining chapters and appendixes. the remainder of this chapter provides references to related documentation. chapter 2 architectural overview compares the features of the 8xc196l x microcon- troller family with those of the 8xc196k x microcontroller family and describes the 87c196la, lb internal clock circuitry. chapter 3 address space describes the addressable memory space of the 52-pin 8xc196l x , lists the peripheral special-function registers (sfrs), and provides tables of wsr values for windowing higher memory into the lower register file for direct access. chapter 4 standard and pts interrupts describes the additional interrupts for the 87c196lbs j1850 communications controller peripheral and the sfrs that support those inter- rupts. chapter 5 i/o ports describes the port differences and explains the change in the port reset state from a logic 1 to a logic 0 on the 87c196la, lb. chapter 6 synchronous serial i/o port describes the enhanced synchronous serial i/o (ssio) port and explains how to program the two additional peripheral sfrs. chapter 7 event processor array describes the event processor array channel differenc- es. chapter 8 j1850 communications controller describes the 87c196lbs integrated j1850 controller and explains how to configure it. chapter 9 minimum hardware considerations describes device reset options through the reset source register, and discusses hardware design considerations. chapter 10 special operating modes illustrates the internal clock control circuitry of the 87c196la, lb and describes how to enter and exit on-circuit emulation (once) mode. chapter 11 programming the nonvolatile memory describes the memory maps and rec- ommended circuits to support programming of the 87c196la, lbs 24 kbytes of otprom. 8xc196l x supplement 1-2 appendix a signal descriptions provides reference information for the 8xc196l x de- vice pins, including descriptions of the pin functions, reset status of the i/o and control pins, and package pin assignments. glossary defines terms with special meaning used throughout this supplement. index lists key topics with page number references. 1.2 related documents table 1-1 lists additional documents that you may find useful in designing systems incorporating the 8xc196l x microcontrollers. table 1-1. related documents title and description order number 8xc196kx, 8xc196jx, 87c196ca microcontroller family users manual 272258 87c196la-20 mhz chmos 16-bit microcontroller automotive datasheet 272806 87c196lb-20 mhz chmos 16-bit microcontroller automotive datasheet 272807 83c196ld chmos 16-bit microcontroller automotive datasheet 272805 2 architectural overview 2-1 chapter 2 architectural overview this chapter describes architectural differences between the 8xc196l x (87c196la, 87c196lb, and 83c196ld) and the 8xc196k x (8xc196k x , 8xc196j x , and 87c196ca) microcontroller families. both the 8xc196l x and the 8xc196k x are designed for high-speed calculations and fast i/o, and share a common architecture and instruction set with few deviations. this chapter provides a high-level overview of the deviations between the two families. note this supplement describes two product families within the mcs ? 96 microcontroller family. for brevity, the name 8xc196l x is used when the discussion applies to all three l x controllers. likewise, the name 8xc196k x is used when the discussion applies to all the k x , j x , and ca controllers. 2.1 microcontroller features table 2-1 lists the features of the 8xc196l x and the 8xc196k x . table 2-1. features of the 8xc196l x and 8xc196k x product famiies device pins otprom/ eprom/ rom (1) register ram (2) code ram i/o pins epa pins sio/ ssio ports a/d can j1850 ext. interrupt pins 87c196la 52 24 k 768 416 3 6 1 87c196lb 52 24 k 768 41 6 3 6 1 1 83c196ld 52 16 k 384 41 6 3 1 8xc196jv 52 48 k 1536 512 41 6 3 6 1 8xc196kt 68 32 k 1024 512 56 10 3 8 2 8xc196jt 52 32 k 1024 512 41 6 3 6 1 87c196ca 68 32 k 1024 256 51 6 3 6 1 2 8xc196kr 68 16 k 512 256 56 10 3 8 2 8xc196jr 52 16 k 512 256 41 6 3 6 1 notes: 1. optional. the second character of the device name indicates the presence and type of nonvolatile memory. 80c196 xx = none; 83c196 xx = rom; 87c196 xx = otprom or eprom. 2. register ram amounts include the 24 bytes allocated to core sfrs and the stack pointer. 8xc196l x supplement 2-2 2.2 block diagram figure 2-1 is a simplified block diagram that shows the major blocks within the microcontroller. observe that the slave port peripheral does not exist on the 8xc196l x . figure 2-1. 8xc196l x block diagram 2.3 internal timing the 87c196la, lb clock circuitry (figure 2-2) implements a phase-locked loop and clock mul- tiplier circuitry, which can substantially increase the cpu clock rate while using a lower-frequen- cy input clock. the clock circuitry accepts an input clock signal on xtal1 provided by an external crystal or oscillator. depending on the value of the pllen pin, this frequency is routed either through the phase-locked loop and multiplier or directly to the divide-by-two circuit. the multiplier circuitry can double the input frequency (f xtal 1 ) before the frequency (f) reaches the divide-by-two circuitry. the clock generators accept the divided input frequency (f/2) from the divide-by-two circuit and produce two nonoverlapping internal timing signals, ph1 and ph2. these signals are active when high. note this manual uses lowercase f to represent the internal clock frequency. for the 87c196la and lb, f is equal to either f xtal 1 or 2f xtal 1 , depending on the clock multiplier mode, which is controlled by the pllen input pin. a5253-01 optional rom/ otprom core (cpu, memory controller) optional code/data ram clock and power mgmt. peripheral transaction server epa a/d ssio i/o wdt sio j1850 interrupt controller note: the j1850 peripheral is unique to the 87c196lb device. the a/d peripheral is unique to the 87c196la, lb devices. 2-3 architectural overview figure 2-2. clock circuitry (87c196la, lb only) the rising edges of ph1 and ph2 generate the internal clkout signal (figure 2-3). the clock circuitry routes separate internal clock signals to the cpu and the peripherals to provide flexibil- ity in power management. it also outputs the clkout signal on the clkout pin. because of the complex logic in the clock circuitry, the signal on the clkout pin is a delayed version of the internal clkout signal. this delay varies with temperature and voltage. phase-locked loop clock multiplier phase comparator filter phase-locked oscillator a5290-01 disable pll (powerdown) xtal1 xtal2 f xtal1 disable oscillator (powerdown) 0 1 disable clocks (idle, powerdown) 1 0 pllen 2f xtal1 clock generators programmable divider (clk1:0) disable clock input (powerdown) cpu clocks (ph1, ph2) peripheral clocks (ph1, ph2) disable clocks (powerdown) clkout f f/2 osc f xtal1 f/2 divide by two circuit clock failure detection to reset logic 8xc196l x supplement 2-4 figure 2-3. internal clock phases (assumes pll is bypassed) the combined period of phase 1 and phase 2 of the internal clkout signal defines the basic time unit known as a state time or state . table 2-2 lists state time durations at various frequencies. the following formulas calculate the frequency of ph1 and ph2, the duration of a state time, and the duration of a clock period (t). because the device can operate at many frequencies, this manual defines time requirements (such as instruction execution times) in terms of state times rather than specific measurements. datasheets list ac characteristics in terms of clock periods (t; sometimes called t osc ). figure 2-4 illustrates the timing relationships between the input frequency (f xtal 1 ), the operating frequency (f), and the clkout signal with each pllen pin configuration. table 2-3 details the relationships between the input frequency (f xtal 1 ), the pllen pin, the operating frequency (f), the clock period (t), and state times. table 2-2. state times at various frequencies f (frequency input to the divide-by-two circuit) state time 8 mhz 250 ns 12 mhz 167 ns 16 mhz 125 ns 20 mhz 100 ns ph1 ph2 clkout phase 1 phase 2 xtal1 a0805-01 1 state time phase 1 phase 2 tt 1 state time ph1 (in mhz) f 2 -- - ph2 == state time (in s) 2 f -- - = t 1 f -- - = 2-5 architectural overview figure 2-4. effect of clock mode on internal clkout frequency 2.4 external timing you can control the output frequency on the clkout pin by programming two uneraseable prom bits. figure 2-5 illustrates the read-only usfr1, which reflects the state of the unerasable prom bits. you can select one of three frequencies: f/2, f/4, or f/8. as figure 2-2 on page 2-3 shows, the configurable divider accepts the output of the clock generators (f/2) and further di- vides that frequency to produce the desired output frequency. the clk1:0 bits control the divisor (divide f/2 by either 1, 2, or 4). table 2-3. relationships between input frequency, clock multiplier, and state times f xtal 1 (frequency on xtal1) pllen multiplier f (input frequency to the divide-by-two circuit) t (clock period) state time 4 mhz 0 1 4 mhz 250 ns 500 ns 8 mhz 0 1 8 mhz 125 ns 250 ns 12 mhz 0 1 12 mhz 83.5 ns 167 ns 16 mhz 0 1 16 mhz 62.5 ns 125 ns 20 mhz 0 1 20 mhz 50 ns 100 ns 4 mhz 1 2 8 mhz 125 ns 250 ns 8 mhz 1 2 16 mhz 62.5 ns 125 ns 10 mhz 1 2 20 mhz 50 ns 100 ns internal clkout internal clkout t = 62.5ns t = 31.25ns t xhch xtal1 (16 mhz) f pllen = 1 f pllen = 0 a3376-01 8xc196l x supplement 2-6 to program these bits, write the correct value to the locations shown in table 2-4 using slave pro- gramming mode. during normal operation, you can determine the values of these bits by reading the uprom sfr (figure 2-5). you can verify a uprom bit to make sure it programmed, but you cannot erase it. for this rea- son, intel cannot test the bits before shipment. however, intel does test the features that the up- rom bits enable, so the only undetectable defects are (unlikely) defects within the uprom cells themselves. 2.5 internal peripherals the internal peripheral modules provide special functions for a variety of applications. this sec- tion provides a brief description of the peripherals that differ between the 8xc196l x and the 8xc196k x families. usfr1 (read only) address: reset state: 1ff2h xxh the uprom special-function register 1 (usfr1) reflects the status of unerasable, programmable read-only memory (uprom) locations. this read-only register reflects the status of two bits that control the output frequency on clkout. 7 0 clk1 clk0 bit number bit mnemonic function 7:2 reserved. 1:0 clk1:0 clkout control these bits reflect the programmed frequency of the clkout signal: clk1 clk0 0 0 divide by 1 (clkout = f/2) 0 1 divide by 2 (clkout = f/4) 1 0 divide by 4 (clkout = f/8) 1 1 divide by 1 (clkout = f/2) figure 2-5. unerasable prom 1 (usfr1) register (la, lb only) table 2-4. uprom programming values and locations to set this bit write this value to this location clk0 0001h 0768h clk1 0002h 0728h 2-7 architectural overview 2.5.1 i/o ports the i/o ports of the 8xc196l x are functionally identical to those of the 8xc196j x . however, on the 87c196la and lb the reset state level of all 41 general-purpose i/o pins has changed from a weak logic 1 (wk1) to a weak logic 0 (wk0). 2.5.2 synchronous serial i/o port the synchronous serial i/o (ssio) port on the 8xc196l x has been enhanced, implementing two new special function registers (ssio0_clk and ssio1_clk) that allow you to select the oper- ating mode and configure the phase and polarity of the serial clock signals. 2.5.3 event processor array the 8xc196l x s event processor array (epa) is functionally identical to that of the 8xc196j x , except that it has only two epa capture/compare channels without pins instead of four. in addi- tion the ld has no compare-only channels. 2.5.4 j1850 communications controller the 87c196lb microcontroller has a peripheral not found on the 8xc196k x microcontrollers or any other l x microcontroller, the j1850 peripheral. the j1850 communications controller man- ages communications between multiple network nodes. this integrated peripheral supports the 10.4 kb/s vpw (variable pulse-width) medium-speed, class b, in-vehicle network protocol. it also supports both the standard and in-frame response (ifr) message framing as specified by the society of automotive engineering ( sae) j1850 (revised may 1994) technical standards. 2.6 design considerations with the exception of a few new multiplexed functions, the 8xc196l x microcontrollers are pin compatible with the 8xc196j x microcontrollers. the 8xc196j x microcontrollers are 52-lead versions of 8xc196k x microcontrollers. for registers that are implemented in both the 8xc196l x and the 8xc196j x , configure the 8xc196l x register as you would for the 8xc196j x unless differences are noted in this supplement. 3 address space 3-1 chapter 3 address space this chapter describes the differences in the address space of the 8xc196l x from that of the 8xc196k x . 3.1 address partitions table 3-1 is an address map of the 8xc196l x and 8xc196k x microcontroller family members. table 3-1. address map device and hex address range description addressing modes ca jr, kr ld la, lb jt, kt jv ffff a000 ffff 6000 ffff 6000 ffff 8000 ffff a000 ffff e000 external device (memory or i/o) connected to address/data bus indirect or indexed 9fff 2080 5fff 2080 5fff 2080 7fff 2080 9fff 2080 dfff 2080 program memory (internal nonvolatile or external memory); see note 1 indirect or indexed 207f 2000 207f 2000 207f 2000 207f 2000 207f 2000 207f 2000 special-purpose memory (internal nonvolatile or external memory) indirect or indexed 1fff 1fe0 1fff 1fe0 1fff 1fe0 1fff 1fe0 1fff 1fe0 1fff 1fe0 memory-mapped sfrs indirect or indexed 1fdf 1f00 1fdf 1f00 1fdf 1f00 1fdf 1f00 1fdf 1f00 1fdf 1f00 peripheral sfrs (includes j1850 sfrs on 87c196lb) indirect, indexed, or windowed direct 1eff 1e00 can sfrs indirect, indexed, or windowed direct 1dff 1c00 1eff 1c00 1eff 1c00 1eff 0300 1eff 1c00 1eff 1e00 external device (memory or i/o) connected to address/data bus; (future sfr expansion; see note 2) indirect or indexed 1dff 1c00 register ram indirect, indexed, or windowed direct notes: 1. after a reset, the device fetches its first instruction from 2080h. 2. the content or function of these locations may change in future device revisions, in which case a program that relies on a location in this range might not function properly. 8xc196l x supplement 3-2 3.2 register file figure 3-1 compares the register file addresses of the 8xc196l x and 8xc196k x . the register file in figure 3-1 is divided into an upper register file and a lower register file. the upper register file consists of general-purpose register ram. the lower register file contains general-purpose register ram along with the stack pointer (sp) and the cpu special-function registers (sfrs). table 3-2 lists the register file memory addresses. the ralu accesses the lower register file di- rectly, without the use of the memory controller. it also accesses a windowed location directly (see windowing on page 3-6). the upper register file and the peripheral sfrs can be win- dowed. registers in the lower register file and registers being windowed can be accessed with register-direct addressing. note the register file must not contain code. an attempt to execute an instruction from a location in the register file causes the memory controller to fetch the instruction from external memory. 1bff 0500 1bff 0500 1bff 0600 1bff 0600 1bff 0600 external device (memory or i/o) connected to address/data bus indirect or indexed 04ff 0400 04ff 0400 05ff 0400 05ff 0400 internal code or data ram indirect or indexed 03ff 0200 05ff 0180 external device (memory or i/o) connected to address/data bus indirect or indexed 03ff 0100 01ff 0100 017f 0100 02ff 0100 03ff 0100 03ff 0100 upper register file (general-purpose register ram) indirect, indexed, or windowed direct 00ff 0000 00ff 0000 00ff 0000 00ff 0000 00ff 0000 00ff 0000 lower register file (register ram, stack pointer, and cpu sfrs) direct, indirect, or indexed table 3-1. address map (continued) device and hex address range description addressing modes ca jr, kr ld la, lb jt, kt jv notes: 1. after a reset, the device fetches its first instruction from 2080h. 2. the content or function of these locations may change in future device revisions, in which case a program that relies on a location in this range might not function properly. 3-3 address space figure 3-1. register file address map table 3-2. register file memory addresses device and hex address range description addressing modes jv ca,jt,kt la, lb jr, kr ld 1dff 1c00 register ram indirect, indexed, or windowed direct 03ff 0100 03ff 0100 02ff 0100 01ff 0100 017f 0100 upper register file (register ram) indirect, indexed, or windowed direct 00ff 001a 00ff 001a 00ff 001a 00ff 001a 00ff 001a lower register file (register ram) direct, indirect, or indexed 0019 0018 0019 0018 0019 0018 0019 0018 0019 0018 lower register file (stack pointer) direct, indirect, or indexed 0017 0000 0017 0000 0017 0000 0017 0000 0017 0000 lower register file (cpu sfrs) direct, indirect, or indexed upper register file lower register file 03ffh 0100h 00ffh 0000h address a5260-01 001ah 0019h 0018h 0017h 0000h general-purpose register ram stack pointer general-purpose register ram cpu sfrs 03ffh (ca, jt, jv, kt) address 0100h 00ffh 017fh (ld) 02ffh (la, lb) 01ffh (jr, kr) 8xc196l x supplement 3-4 3.3 peripheral special-function registers table 3-3 lists the peripheral sfr addresses. highlighted addresses are unique to the 8xc196l x . table 3-3. 8xc196l x peripheral sfrs ports 3, 4, 5, and uprom sfrs ports 0, 1, 2, and 6 sfrs address high (odd) byte low (even) byte address high (odd) byte low (even) byte 1ffeh p4_pin p3_pin 1fdeh reserved reserved 1ffch p4_reg p3_reg 1fdch reserved reserved 1ffah slp_con slp_cmd 1fdah reserved p0_pin 1ff8h reserved slp_stat 1fd8h reserved reserved 1ff6h p5_pin usfr 1fd6h p6_pin p1_pin 1ff4h p5_reg p34_drv 1fd4h p6_reg p1_reg 1ff2h p5_dir usfr1 (la, lb) 1fd2h p6_dir p1_dir 1ff0h p5_mode reserved 1fd0h p6_mode p1_mode 1feeh reserved reserved 1fceh p2_pin reserved 1fech reserved reserved 1fcch p2_reg reserved 1feah reserved reserved 1fcah p2_dir reserved 1fe8h reserved reserved 1fc8h p2_mode reserved 1fe6h reserved reserved 1fc6h reserved reserved 1fe4h reserved reserved 1fc4h reserved reserved 1fe2h reserved reserved 1fc2h reserved reserved 1fe0h reserved reserved 1fc0h reserved reserved ? must be addressed as a word. 3-5 address space sio and ssio sfrs epa sfrs (continued) address high (odd) byte low (even) byte address high (odd) byte low (even) byte 1fbeh reserved reserved ? 1f7eh epa7_time (h) epa7_time (l) 1fbch sp_baud (h) sp_baud (l) 1f7ch reserved epa7_con 1fbah sp_con sbuf_tx ? 1f7ah epa6_time (h) epa6_time (l) 1fb8h sp_status sbuf_rx 1f78h reserved epa6_con 1fb6h ssio1_clk reserved ? 1f76h epa5_time (h) epa5_time (l) 1fb4h ssio0_clk ssio_baud 1f74h reserved epa5_con 1fb2h ssio1_con ssio1_buf ? 1f72h epa4_time (h) epa4_time (l) 1fb0h ssio0_con ssio0_buf 1f70h reserved epa4_con a/d sfrs (la, lb only) ? 1f6eh epa3_time (h) epa3_time (l) address high (odd) byte low (even) byte ? 1f6ch epa3_con (h) epa3_con (l) 1faeh ad_time ad_test ? 1f6ah epa2_time (h) epa2_time (l) 1fach reserved ad_command 1f68h reserved epa2_con 1faah ad_result (h) ad_result (l) ? 1f66h epa1_time (h) epa1_time (l) epa interrupt sfrs ? 1f64h epa1_con (h) epa1_con (l) address high (odd) byte low (even) byte ? 1f62h epa0_time (h) epa0_time (l) 1fa8h reserved epaipv 1f60h reserved epa0_con 1fa6h reserved epa_pend1 j1850 sfrs (lb only) 1fa4h reserved epa_mask1 address high (odd) byte low (even) byte ? 1fa2h epa_pend (h) epa_pend (l) 1f5eh reserved reserved ? 1fa0h epa_mask (h) epa_mask (l) 1f5ch reserved reserved timer 1, timer 2, and epa sfrs 1f5ah reserved reserved address high (odd) byte low (even) byte 1f58h reserved j_dly ? 1f9eh timer2 (h) timer2 (l) 1f56h reserved reserved 1f9ch reserved t2control 1f54h reserved j_cfg ? 1f9ah timer1 (h) timer1 (l) 1f52h j_stat j_rx 1f98h reserved t1control 1f50h j_cmd j_tx 1f96h reserved reserved 1f94h reserved reserved 1f92h reserved rst_src 1f90h reserved reserved epa sfrs address high (odd) byte low (even) byte ? 1f8eh comp1_time (h) comp1_time (l) 1f8ch reserved comp1_con ? 1f8ah comp0_time (h) comp0_time (l) 1f88h reserved comp0_con ? 1f86h epa9_time (h) epa9_time (l) 1f84h reserved epa9_con ? 1f82h epa8_time (h) epa8_time (l) 1f80h reserved epa8_con table 3-3. 8xc196l x peripheral sfrs (continued) ? must be addressed as a word. 8xc196l x supplement 3-6 3.4 windowing windowing maps a segment of higher memory (the upper register file or peripheral sfrs) into the lower register file. the window selection register (wsr) selects a 32-, 64- or 128-byte seg- ment of higher memory to be windowed into the top of the lower register file space. table 3-4 lists the wsr values for windowing the upper register file for both the 8xc196l x and 8xc196k x . table 3-4. windows base address wsr value for 32-byte window (00e0C00ffh) wsr value for 64-byte window (00c0C00ffh) wsr value for 128-byte window (0080C00ffh) peripheral sfrs 1fe0h 7fh (note) 3fh (note) 1fh (note) 1fc0h 7eh 1fa0h 7dh 3eh 1f80h 7ch 1f60h 7bh 3dh 1eh 1f40h 7ah 1f20h 79h 3ch 1f00h 78h can peripheral sfrs (87c196ca only) 1ee0h 77h 3bh 1dh 1ec0h 76h 1ea0h 75h 3ah 1e80h 74h 1e60h 73h 39h 1ch 1e40h 72h 1e20h 71h 38h 1e00h 70h register ram (87c196jv only) 1de0h 6fh 37h 1bh 1dc0h 6eh 1da0h 6dh 36h 1d80h 6ch 1d60h 6bh 35h 1ah 1d40h 6ah 1d20h 69h 34h 1d00h 68h note: locations 1fe0C1fffh contain memory-mapped sfrs that cannot be accessed through a window. reading these locations through a window returns ffh; writing these locations through a window has no effect. 3-7 address space register ram (87c196jv only; continued) 1ce0h 67h 33h 19h 1cc0h 66h 1ca0h 65h 32h 1c80h 64h 1c60h 63h 31h 18h 1c40h 62h 1c20h 61h 30h 1c00h 60h upper register file (ca, jt, jv, kt) 03e0h 5fh 2fh 17h 03c0h 5eh 03a0h 5dh 2eh 0380h 5ch 0360h 5bh 2dh 16h 0340h 5ah 0320h 59h 2ch 0300h 58h upper register file (ca, jt, jv, kt, la, lb) 02e0h 57h 2bh 15h 02c0h 56h 02a0h 55h 2ah 0280h 54h 0260h 53h 29h 14h 0240h 52h 0220h 51h 28h 0200h 50h upper register file (ca, jr, jt, jv, kr, kt, la, lb) 01e0h 4fh 27h 13h 01c0h 4eh 01a0h 4dh 26h 0180h 4ch table 3-4. windows (continued) base address wsr value for 32-byte window (00e0C00ffh) wsr value for 64-byte window (00c0C00ffh) wsr value for 128-byte window (0080C00ffh) note: locations 1fe0C1fffh contain memory-mapped sfrs that cannot be accessed through a window. reading these locations through a window returns ffh; writing these locations through a window has no effect. 8xc196l x supplement 3-8 upper register file (ca, jr, jt, jv, kr, kt, la, lb, ld) 0160h 4bh 25h 12h 0140h 4ah 0120h 49h 24h 0100h 48h table 3-4. windows (continued) base address wsr value for 32-byte window (00e0C00ffh) wsr value for 64-byte window (00c0C00ffh) wsr value for 128-byte window (0080C00ffh) note: locations 1fe0C1fffh contain memory-mapped sfrs that cannot be accessed through a window. reading these locations through a window returns ffh; writing these locations through a window has no effect. 4 standard and pts interrupts 4-1 chapter 4 standard and pts interrupts the interrupt structure of the 8xc196l x is the same as that of the 8xc196j x . the only difference is that the slave port interrupts (int08:06) now support the j1850 controller peripheral. 4.1 interrupt sources, vectors, and priorities table 4-1 lists the 8xc196lxs interrupts sources, default priorities (30 is highest and 0 is low- est), and vector addresses. 8xc196l x supplement 4-2 4.2 interrupt registers this section describes the changes in the interrupt register bit definitions for the 8xc196l x fam- ily. table 4-1. interrupt sources, vectors, and priorities interrupt source mnemonic interrupt controller service pts service name vector priority ? name vector priority nonmaskable interrupt nmi ? int15 203eh 30 extint pin extint int14 203ch 14 pts14 205ch 29 reserved int13 203ah 13 pts13 205ah 28 sio receive ri int12 2038h 12 pts12 2058h 27 sio transmit ti int11 2036h 11 pts11 2056h 26 ssio channel 1 transfer ssio1 int10 2034h 10 pts10 2054h 25 ssio channel 0 transfer ssio0 int09 2032h 09 pts09 2052h 24 j1850 status (lb only) j1850st int08 2030h 08 pts08 2050h 23 reserved (la, ld) int08 2030h 08 pts08 2050h 23 unimplemented opcode 2012h software trap instruction 2010h j1850 receive (lb only) j1850rx int07 200eh 07 pts07 204eh 22 reserved (la, ld) int07 200eh 07 pts07 204eh 22 j1850 transmit (lb only) j1850tx int06 200ch 06 pts06 204ch 21 reserved (la, ld) int06 200ch 06 pts06 204ch 21 a/d conv. complete (la, lb) ad_done int05 200ah 05 pts05 204ah 20 reserved (ld) int05 200ah 05 pts05 204ah 20 epa capture/compare 0 epa0 int04 2008h 04 pts04 2048h 19 epa capture/compare 1 epa1 int03 2006h 03 pts03 2046h 18 epa capture/compare 2 epa2 int02 2004h 02 pts02 2044h 17 epa capture/compare 3 epa3 int01 2002h 01 pts01 2042h 16 epa capture/compare 6C9, epa 0C3, 8C9 overrun, epa compare 0C1 ??? , timer 1 overflow, & timer 2 overflow epa x ?? int00 2000h 00 pts00 2040h 15 ? the nmi pin is not bonded out on the 8xc196l x . to protect against glitches, create a dummy interrupt service routine that contains a ret instruction. ?? these interrupts are individually prioritized in the epaipv register. read the epa pending registers (epa_pend and epa_pend1) to determine which source caused the interrupt. ??? 87c196la, lb only. the 83c196ld has no epa compare-only channels. 4-3 standard and pts interrupts 4.2.1 interrupt mask registers figures 4-1 and 4-2 illustrate the interrupt mask registers for the 8xc196l x microcontrollers. int_mask address: reset state: 0008h 00h the interrupt mask (int_mask) register enables or disables (masks) individual interrupt requests. (the ei and di instructions enable and disable servicing of all maskable interrupts.) int_mask is the low byte of the processor status word (psw). pushf or pusha saves the contents of this register onto the stack and then clears this register. interrupt calls cannot occur immediately following a push instruction. popf or popa restores it. 7 0 la ad epa0 epa1 epa2 epa3 epa x 7 0 lb j1850rx j1850tx ad epa0 epa1 epa2 epa3 epa x 7 0 ld epa0 epa1 epa2 epa3 epa x bit number function 7:0 ? setting a bit enables the corresponding interrupt. bit mnemonic interrupt description j1850rx j1850 receive (lb only) j1850tx j1850 transmit (lb only) ad a/d conversion complete (la, lb) epa0 epa capture/compare channel 0 epa1 epa capture/compare channel 1 epa2 epa capture/compare channel 2 epa3 epa capture/compare channel 3 epa x ?? shared epa interrupt ?? epa 6C9 capture/compare channel events, epa 0C1 compare channel events ??? , epa 0C3 and 8C9 capture/compare overruns, and timer overflows can generate this multiplexed interrupt. the epa mask and pending registers decode the epa x interrupt. write the epa mask registers to enable the interrupt sources; read the epa pending registers to determine which source caused the interrupt. ??? 87c196la, lb only. ? bits 6C7 are reserved on the 87c196la, and bits 5C7 are reserved on the 83c196ld. for compatibility with future devices, write zeros to these bits. figure 4-1. interrupt mask (int_mask) register 8xc196l x supplement 4-4 4.2.2 interrupt pending registers figures 4-3 and 4-4 illustrate the interrupt pending registers for the 8xc196l x microcontrollers. int_mask1 address: reset state: 0013h 00h the interrupt mask 1 (int_mask1) register enables or disables (masks) individual interrupt requests. (the ei and di instructions enable and disable servicing of all maskable interrupts.) int_mask1 can be read from or written to as a byte register. pusha saves this register on the stack and popa restores it. 7 0 lb nmi extint ri ti ssio1 ssio0 j1850st 7 0 la, ld nmi extint ri ti ssio1 ssio0 bit number function 7:0 ? setting a bit enables the corresponding interrupt. bit mnemonic interrupt description nmi ?? nonmaskable interrupt extint extint pin reserved ri sio receive ti sio transmit ssio1 ssio1 transfer ssio0 ssio0 transfer j1850st j1850 status (lb only) ?? nmi is always enabled. this nonfunctional mask bit exists for design symmetry with the int_pend1 register. always write zero to this bit. ? bit 5 is reserved on the 8xc196l x devices, and bit 0 is reserved on the 87c196la and 83c196ld. for compatibility with future devices, always write zeros to these bits. figure 4-2. interrupt mask 1 (int_mask1) register 4-5 standard and pts interrupts int_pend address: reset state: 0009h 00h when hardware detects an interrupt request, it sets the corresponding bit in the interrupt pending (int_pend or int_pend1) registers. when the vector is taken, the hardware clears the pending bit. software can generate an interrupt by setting the corresponding interrupt pending bit. 7 0 la ad epa0 epa1 epa2 epa3 epa x 7 0 lb j1850rx j1850tx ad epa0 epa1 epa2 epa3 epa x 7 0 ld epa0 epa1 epa2 epa3 epa x bit number function 7:0 ? any set bit indicates that the corresponding interrupt is pending. the interrupt bit is cleared when processing transfers to the corresponding interrupt vector. bit mnemonic interrupt description j1850rx j1850 receive (lb only) j1850tx j1850 transmit (lb only) ad a/d conversion complete (la, lb) epa0 epa capture/compare channel 0 epa1 epa capture/compare channel 1 epa2 epa capture/compare channel 2 epa3 epa capture/compare channel 3 epa x ?? shared epa interrupt ?? epa 6C9 capture/compare channel events, epa 0C1 compare channel events ??? , epa 0C3 and 8C9 capture/compare overruns, and timer overflows can generate this shared interrupt. write the epa mask registersto enable the interrupt sources; read the epa pending registers to determine which source caused the interrupt. ??? 87c196la, lb only. ? bits 6C7 are reserved on the 87c196la, and bits 5C7 are reserved on the 83c196ld. for compatibility with future devices, write zeros to these bits. figure 4-3. interrupt pending (int_pend) register 8xc196l x supplement 4-6 4.2.3 peripheral transaction server registers figures 4-5 and 4-6 illustrate the pts interrupt select and service registers for the 8xc196l x mi- crocontrollers. int_pend1 address: reset state: 0012h 00h when hardware detects an interrupt request, it sets the corresponding bit in the interrupt pending (int_pend or int_pend1) registers. when the vector is taken, the hardware clears the pending bit. software can generate an interrupt by setting the corresponding interrupt pending bit. 7 0 lb nmi extint ri ti ssio1 ssio0 j1850st 7 0 la, ld nmi extint ri ti ssio1 ssio0 bit number function 7:0 ? any set bit indicates that the corresponding interrupt is pending. the interrupt bit is cleared when processing transfers to the corresponding interrupt vector. bit mnemonic interrupt description nmi nonmaskable interrupt extint extint pin reserved ri sio receive ti sio transmit ssio1 ssio 1 transfer ssio0 ssio 0 transfer j1850st j1850 status (lb only) ? bit 5 is reserved on the 8xc196l x devices and bit 0 is reserved on the 87c196la and 83c196ld. for compatibility with future devices, always write zeros to these bits. figure 4-4. interrupt pending 1 (int_pend1) register 4-7 standard and pts interrupts ptssel address: reset state: 0004h 0000h the pts select (ptssel) register selects either a pts microcode routine or a standard interrupt service routine for each interrupt request. setting a bit selects a pts microcode routine; clearing a bit selects a standard interrupt service routine. in pts modes that use the ptscount register, hardware clears the corresponding ptssel bit when ptscount reaches zero. the end-of-pts interrupt service routine must reset the ptssel bit to re-enable the pts channel. 15 8 la extint ri ti ssio1 ssio0 7 0 ad epa0 epa1 epa2 epa3 epa x 15 8 lb extint ri ti ssio1 ssio0 j1850st 7 0 j1850rx j1850tx ad epa0 epa1 epa2 epa3 epa x 15 8 ld extint ri ti ssio1 ssio0 7 0 epa0 epa1 epa2 epa3 epa x bit number function 14:0 ? setting a bit causes the corresponding interrupt to be handled by a pts microcode routine. the pts interrupt vector locations are as follows: bit mnemonic interrupt pts vector extint extint pin 205ch reserved ? 205ah ri sio receive 2058h ti sio transmit 2056h ssio1 ssio 1 transfer 2054h ssio0 ssio 0 transfer 2052h j1850st (lb) j1850 status 2050h j1850rx(lb) j1850 receive 204eh j1850tx(lb) j1850 transmit 204ch ad (la, lb) a/d conversion complete 204ah epa0 epa capture/compare channel 0 2048h epa1 epa capture/compare channel 1 2046h epa2 epa capture/compare channel 2 2044h epa3 epa capture/compare channel 3 2042h epa x ?? multiplexed epa 2040h ?? pts service is not useful for shared interrupts because the pts cannot readily determine the source of these interrupts. ? bit 13 is reserved on the 8xc196l x devices and bits 6C8 are reserved on the 87c196la and 83c196ld. for compatibility with future devices, write zeros to these bits. figure 4-5. pts select (ptssel) register 8xc196l x supplement 4-8 ptssrv address: reset state: 0006h 0000h the pts service (ptssrv) register is used by the hardware to indicate that the final pts interrupt has been serviced by the pts routine. when ptscount reaches zero, hardware clears the corresponding ptssel bit and sets the ptssrv bit, which requests the end-of-pts interrupt. when the end-of-pts interrupt is called, hardware clears the ptssrv bit. the end-of-pts interrupt service routine must set the ptssel bit to re-enable the pts channel. 15 8 la extint ri ti ssio1 ssio0 7 0 ad epa0 epa1 epa2 epa3 epa x 15 8 lb extint ri ti ssio1 ssio0 j1850st 7 0 j1850rx j1850tx ad epa0 epa1 epa2 epa3 epa x 15 8 ld extint ri ti ssio1 ssio0 7 0 epa0 epa1 epa2 epa3 epa x bits function 14:0 ? a bit is set by hardware to request an end-of-pts interrupt for the corresponding interrupt through its standard interrupt vector. the standard interrupt vector locations are as follows: bit mnemonic interrupt standard vector extint extint pin 203ch reserved ? 203ah ri sio receive 2038h ti sio transmit 2036h ssio1 ssio 1 transfer 2034h ssio0 ssio 0 transfer 2032h j1850st (lb) j1850 status 2030h j1850rx (lb) j1850 receive 202eh j1850tx (lb) j1850 transmit 202ch ad (la, lb) a/d conversion complete 202ah epa0 epa capture/compare channel 0 2028h epa1 epa capture/compare channel 1 2026h epa2 epa capture/compare channel 2 2024h epa3 epa capture/compare channel 3 2022h epa x ?? multiplexed epa 2020h ?? pts service is not useful for shared interrupts because the pts cannot readily determine the source of these interrupts. ? bit 13 is reserved on the 8xc196l x devices and bits 6C8 are reserved on the 87c196la and 83c196ld. for compatibility with future devices, write zeros to these bits. figure 4-6. pts service (ptssrv) register 5 i/o ports 5-1 chapter 5 i/o ports the i/o ports of the 8xc196l x are functionally identical to those of the 8xc196j x . however, on the 87c196la and lb, the reset state level of all 41 general-purpose i/o pins has changed from a weak logic 1 (wk1) to a weak logic 0 (wk0). this chapter outlines the differences between the 87c196la, lb and the 8xc196k x controllers. 5.1 i/o ports overview table 5-1 provides an overview of the 8xc196l x and 8xc196k x i/o ports. 5.2 internal structure for ports 1, 2, 5, and 6 (bidirectional ports) figure 5-1 shows the logic for driving the output transistors, q1 and q2. consult the datasheet for specifications on the amount of current that each port can source or sink. in i/o mode (selected by clearing a port mode register bit ) , the port data output and the port di- rection registers are input to the multiplexers. these signals combine to drive the gates of q1 and q2 so that the output is high, low, or high impedance. in special-function mode (selected by setting a port mode register bit), sfdir and sfdata are input to the multiplexers. these signals combine to drive the gates of q1 and q2 so that the output is high, low, or high impedance. special-function output signals clear sfdir; special-function table 5-1. microcontroller ports port pins type configuration options associated peripheral or system function port 0 8 (k x ) 6 (ca, j x, l x ) standard input-only a/d converter (not supported on ld) port 1 8 (k x ) 4 (ca, j x, l x ) standard complementary open-drain epa and timers port 2 8 (k x ) 6 (ca, j x, l x ) standard complementary open-drain j1850 (lb only), sio, interrupts, bus control, clock gen. port 3 8 memory mapped complementary open-drain address/data bus port 4 8 memory mapped complementary open-drain address/data bus port 5 8 (k x ) 3 (ca, j x, l x ) memory mapped complementary open-drain bus control, slave port port 6 8 (k x ) 6 (ca, j x, l x ) standard complementary open-drain epa, ssio 8xc196l x supplement 5-2 input signals set sfdir. even if a pin is to be used in special-function mode, you must still ini- tialize the pin as an input or output by writing to the port direction register. resistor r1 provides esd protection for the pin. input signals are buffered. the standard ports use schmitt-triggered buffers for improved noise immunity. port 5 uses a standard input buffer because of the high speeds required for bus control functions. the signals are latched into the port pin register sample latch and output onto the internal bus when the port pin register is read. the falling edge of reset# turns on transistor q3, which remains on for about 300 ns, causing the pin to change rapidly to its reset state. the active-low level of reset# turns on transistor q4, which weakly holds the pin low. q4 remains on, weakly holding the pin low, until your software writes to the port mode register. note p2.7 is an exception. after reset, p2.7 carries the clkout signal (half the crystal input frequency) rather than being held low. when clkout is selected, it is always a complementary output. 5-3 i/o ports figure 5-1. ports 1, 2, 5, and 6 internal structure (87c196la, lb only) 5.2.1 configuring ports 1, 2, 5, and 6 (bidirectional ports) using the port mode register, you can individually configure each pin for port 1, 2, 5, and 6 to operate either as a general-purpose i/o signal (i/o mode) or as a special-function signal (special- function mode). in either mode, three configurations are possible: complementary output, high- q2 q1 p x _mode p x _drv sfdir 0 1 p x _reg sample latch ph1 clock internal bus sfdata any write to p x _mode q r weak pullup reset# q3 q4 buffer read port s 300ns delay i/o pin reset# a5265-01 150 w to 200 w r1 0 1 v ss medium pullup v ss v ss v cc reset# p x _pin d q le 8xc196l x supplement 5-4 impedance input, or open-drain output. the port direction and data output registers select the con- figuration for each pin. complementary output means that the microcontroller drives the signal high or low. high-impedance input means that the microcontroller floats the signal. open-drain output means that the microcontroller drives the signal low or floats it. for i/o mode, the port data output register determines whether the microcontroller drives the signal high, drives it low, or floats it. for special-function mode, the on-chip peripheral or system function determines whether the microcontroller drives the signal high or low for complementary outputs. the pins for ports 1, 2, 5, and 6 are weakly pulled low during and after reset. initializing the pins by writing to the port mode register turns off the weak pull-downs. to ensure that the ports are initialized correctly, follow this suggested initialization sequence: 1. write to p x _dir to configure the individual pins. clearing a bit configures a pin as a complementary output. setting a bit configures a pin as a high-impedance input or open- drain output. 2. write to p x _mode to select either i/o or special-function mode. writing to p x _mode (regardless of the value written) turns off the weak pull-downs. even if the entire port is to be used as i/o (its default configuration after reset), you must write to p x _mode to ensure that the weak pull-downs are turned off . 3. write to p x _reg. for complementary output configurations: in i/o mode, write the data that is to be driven by the pins to the corresponding p x _reg bits. in special-function mode, the value is immaterial because the on-chip peripheral or system function controls the pin. however, you must still write to p x _reg to initialize the pin. for high-impedance input or open-drain output configurations : in i/o mode, write to p x _reg to either float the pin, making it available as a high impedance input, or pull it low. setting the corresponding p x _reg bit floats the pin; clearing the corresponding p x _reg bit pulls the pin low. in special-function mode, if the on-chip peripheral uses the pin as an input signal, you must set the corresponding p x _reg bit so that the pin can be driven externally. if the on-chip peripheral uses the pin as an output signal, the value of the corresponding p x _reg bit is immaterial because the on- chip peripheral or system function controls the pin. however, you must still write to p x _reg to initialize the pin. 5.2.2 special bidirectional port considerations this section outlines special consideration for using the pins of ports 1, 2, 5, and 6. 1. after reset, your software must configure the device to match the external system. this accomplished by writing appropriate configuration data into p x _mode. writing to p x _mode not only configures the pins but also turns off the transistor that weakly holds the pins low. for this reason, even if your port is to be used as it is configured at reset, you should still write data into p x _mode. 2. p2.6/txj1850 is the enable pin for once mode. because a high input during reset can cause the device to enter once mode or a reserved test mode, caution must be exercised 5-5 i/o ports in using this pin. be certain that your system meets the v ih specifications during reset to prevent inadvertent entry into once mode or a test mode. 3. following reset, p2.7/clkout carries the strongly driven clkout signal. it is not held low. when p2.7/clkout is configured as clkout, it is always a complementary output. 5.3 internal structure for ports 3 and 4 (address/data bus) figure 5-2 shows the logic of ports 3 and 4. consult the datasheet for specifications on the amount of current ports 3 and 4 can source and sink. during reset, the active-low level of reset# turns off q1 and q2 and turns on transistor q4, which weakly holds the pin low. resistor r1 provides esd protection for the pin. during normal operation, the device controls the port through bus control select, an internal control sig- nal. when the device needs to access external memory, it clears bus control select, selecting address/data as the input to the multiplexer. address/data then drives q1 and q2 as complementary outputs. when external memory access is not required, the device sets bus control select, select- ing p x _reg as the input to the multiplexer. p x _reg then drives q1 and q2. if p34_drv is set, q1 and q2 are driven as complementary outputs. if p34_drv is cleared, q1 is disabled and q2 is driven as an open-drain output requiring an external pull-up resistor. with the open-drain con- figuration (bus control select set and p34_drv cleared) and p x _reg set, the pin can be used as an input. the signal on the pin is latched in the p x _pin register. the pins can be read, making it easy to see which pins are driven low by the device and which are driven high by ex- ternal drivers while in open-drain mode. 8xc196l x supplement 5-6 figure 5-2. ports 3 and 4 internal structure (87c196la, lb only) q2 q1 p x _reg p34_drv sample latch ph1 clock internal bus address/data p x _pin d q weak pullup reset# q3 q4 buffer read port le 300ns delay i/o pin bus control select 0 = address/data 1 = i/o reset# a5264-01 150 w to 200 w r1 1 0 v ss medium pullup v ss v ss v cc 6 synchronous serial i/o port 6-1 chapter 6 synchronous serial i/o port the synchronous serial i/o (ssio) port on the 8xc196l x has been enhanced, implementing two new special function registers (ssio0_clk and ssio1_clk) that allow you to select the oper- ating mode and configure the phase and polarity of the serial clock signals. 6.1 ssio 0 clock register the ssio 0 clock (ssio_clk) register selects the phase and polarity for the sc0 clock signal. in standard mode, sc0 is channel 0s clock signal. in duplex and channel-select modes, sc0 is the common clock signal for both ssio channels. ssio0_clk address: reset state: 1fb5h 00h the ssio 0 clock (ssio0_clk) register configures the serial clock for channel 0. in standard mode, the sc0 is channel 0s clock signal. in duplex and channel-select modes, sc0 is the common clock signal for both ssio channels. 7 0 phas pols bit number bit mnemonic function 7:2 reserved; for compatibility with future devices, write zeros to these bits. 1 phas phase and polarity select for normal transfers, these bits determine the idle state of the serial clock and select the serial clock signal edge on which the ssio samples incoming data bits or shifts out outgoing data bits. these bits are ignored for handshaking transfers. use ssio0_ con to select the type of data transfer (normal or handshaking) for channel 0. for transmissions phas pols 0 0 low idle state; shift on falling edges 0 1 high idle state; shift on rising edges 1 0 low idle state; shift on rising edges 1 1 high idle state; shift on falling edges for receptions phas pols 0 0 low idle state; sample on rising edges 0 1 high idle state; sample on falling edges 1 0 low idle state; sample on falling edges 1 1 high idle state; sample on rising edges 0pols figure 6-1. ssio 0 clock (ssio0_clk) register 8xc196l x supplement 6-2 for transmissions, ssio0_clk determines whether the ssio shifts out data bits on rising or fall- ing clock edges. for receptions, ssio0_clk determines whether the ssio samples data bits on rising or falling clock edges. 6.2 ssio 1 clock register ssio1_clk selects the ssio mode of operation (standard, duplex, or channel-select), enables the channel-select master contention interrupt request, and selects the phase and polarity for the serial clock (sc1) for channels. in standard mode, use this register to configure the serial clock for channel 1. ssio1_clk address: reset state: 1fb7h 00h the ssio 1 clock (ssio1_clk) register selects the ssio mode of operation (standard, duplex, or channel-select), enables the channel-select master contention interrupt request, and selects the phase and polarity for the serial clock (sc1) for channel 1. 7 0 chs dup conint conpnd phas pols bit number bit mnemonic function 7:6 reserved; for compatibility with future devices, write zeros to these bits. 5 chs these bits determine the ssio operating mode. chs dup 0 0 standard mode 0 1 duplex mode 1 0 channel-select half-duplex mode (uses sd1 only) 1 1 channel-select full-duplex mode (uses both sd0 and sd1) 4 dup 3 conint master contention interrupt for channel-select master operations, the ssio sets the master contention interrupt pending bit (conpnd) when the chs# pin is externally activated. in a system with multiple masters, an external master activates the chs# signal to request control of the serial clock. conint determines whether the ssio sets both conpnd and the ssio0 interrupt pending bit or only conpnd when the chs# pin is externally activated. 0 = ssio sets only conpnd 1 = ssio sets both conpnd and the ssio0 interrupt pending bit this bit is valid for channel-select master operations and ignored for all other operations. figure 6-2. ssio 1 clock (ssio1_clk) register 6-3 synchronous serial i/o port for transmissions, ssio1_clk determines whether the ssio shifts out data bits on rising or fall- ing clock edges. for receptions, ssio1_clk determines whether the ssio samples data bits on the rising or falling clock edges. 2 conpnd master contention interrupt pending for channel-select master operations, the ssio sets this bit when the chs# pin is externally activated. in a system with multiple masters, an external master activates the chs# signal to request control of the serial clock. this bit is valid for channel-select master operations and ignored for all other operations. 1 phas phase and polarity select for normal transfers, these bits determine the idle state of the serial clock and select the serial clock signal edge that the ssio samples incoming data bits or shifts out outgoing data bits. for transmissions phas pols 0 0 low idle state; shift on falling edges 0 1 high idle state; shift on rising edges 1 0 low idle state; shift on rising edges 1 1 high idle state; shift on falling edges for receptions phas pols 0 0 low idle state; sample on rising edges 0 1 high idle state; sample on falling edges 1 0 low idle state; sample on falling edges 1 1 high idle state; sample on rising edges these bits are ignored for duplex and channel-select modes; these modes use sc0 as the common clock signal. the ssio0_clk register contains the phase and polarity select bits for the sc0 clock signal. these bits are also ignored for handshaking transfers. use ssio1_ con to select the type of data transfer (normal or handshaking) for channel 1. 0pols ssio1_clk (continued) address: reset state: 1fb7h 00h the ssio 1 clock (ssio1_clk) register selects the ssio mode of operation (standard, duplex, or channel-select), enables the channel-select master contention interrupt request, and selects the phase and polarity for the serial clock (sc1) for channel 1. 7 0 chs dup conint conpnd phas pols bit number bit mnemonic function figure 6-2. ssio 1 clock (ssio1_clk) register (continued) 7 event processor array 7-1 chapter 7 event processor array the epa on the 8xc196l x is functionally identical to that of the 8xc196j x ; however, the 8xc196l x has only two capture/compare channels without pins instead of four. in addition, the 83c196ld has no compare-only channels. 7.1 epa functional overview table 7-1 lists the capture/compare (with and without pins) and compare-only channels for each device in the 8xc196l x and 8xc196k x families. the 8xc196l x s epa performs input and output functions associated with two timer/counters, timer 1 and timer 2, as depicted in figures 7-1 and 7-2. table 7-1. epa channels device capture/compare channels with pins capture/compare channels without pins compare-only channels 8xc196la, lb epa3:0 and epa9:8 epa7:6 comp1:0 8xc196ld epa3:0 and epa9:8 epa7:6 87c196ca, 8xc196j x epa3:0 and epa9:8 epa7:4 comp1:0 8xc196k x epa9:0 comp1:0 8xc196l x supplement 7-2 figure 7-1. epa block diagram (87c196la, lb only) indirect interrupt processor logic epa x interrupt a5269-01 timer-counter unit epa9 / comp1 epa8 / comp0 epa 3:0 epa 3:0 interrupts timer1 timer2 compare-only channel 1 capture/compare channel 9 compare-only channel 0 capture/compare channel 8 capture/compare channel 6C7 capture/compare channel 0C3 7-3 event processor array figure 7-2. epa block diagram (83c196ld only) indirect interrupt processor logic epa x interrupt a5281-01 timer1 timer2 timer-counter unit capture/compare channel 9 capture/compare channel 8 capture/compare channel 6C7 capture/compare channel 0C3 epa9 epa8 epa 3:0 epa 3:0 interrupts 8xc196l x supplement 7-4 7.1.1 epa mask registers figures 7-3 and 7-4 illustrate the epa mask registers, epa_mask and epa_mask1, for the 8xc196l x microcontroller family. epa_mask address: reset state: 1fa0h 0000h the epa interrupt mask (epa_mask) register enables or disables (masks) interrupts associated with the shared epa x interrupt. 15 8 lx epa6 epa7 epa8 epa9 ovr0 ovr1 7 0 0vr2 ovr3 ovr8 ovr9 bit number function 15:0 ? setting a bit enables the corresponding interrupt as a epa x interrupt source. the shared epa x interrupt is enabled by setting its interrupt enable bit in the interrupt mask register (int_mask.0 = 1). ? bits 2C5 and 14C15 are reserved on the 8xc196l x device family. for compatibility with future devices, write zeros to these bits. figure 7-3. epa interrupt mask (epa_mask) register epa_mask1 address: reset state: 1fa4h 00h the epa interrupt mask 1 (epa_mask1) register enables or disables (masks) interrupts associated with the multiplexed epa x interrupt. 7 0 comp0 ? comp1 ? ovrtm1 ovrtm2 bit number function 7:4 reserved; for compatibility with future devices, write zeros to these bits. 3:0 ? setting a bit enables the corresponding interrupt as a multiplexed epa x interrupt source. the multiplexed epa x interrupt is enabled by setting its interrupt enable bit in the interrupt mask register (int_mask.0 = 1). ? 87c196la, lb only; reserved on 83c196ld. figure 7-4. epa interrupt mask 1 (epa_mask1) register 7-5 event processor array 7.1.2 epa pending registers figures 7-5 and 7-6 illustrate the epa pending registers, epa_pend and epa_pend1, for the 8xc196l x microcontroller family. epa_pend address: reset state: 1fa2h 0000h when hardware detects a pending epa 6C9 or ovr0C3, 8C9 interrupt request, it sets the corresponding bit in the epa interrupt pending register (epa_pend or epa_pend1). the epaipv register contains a number that identifies the highest priority, active, shared interrupt source. when epaipv is read, the epa interrupt pending bit associated with the epaipv priority value is cleared. 15 8 lx epa6 epa7 epa8 epa9 ovr0 ovr1 7 0 0vr2 ovr3 ovr8 ovr9 bit number function 15:0 ? any set bit indicates that the corresponding epa x interrupt source is pending. the bit is cleared when software reads the epa interrupt priority vector register (epaipv). ? bits 2C5 and 14C15 are reserved on the 8xc196l x device family. for compatibility with future devices, write zeros to these bits. figure 7-5. epa interrupt pending (epa_pend) register epa_pend1 address: reset state: 1fa6h 00h when hardware detects a pending epa x interrupt, it sets the corresponding bit in the epa interrupt pending register (epa_pend or epa_pend1). the epaipv register contains a number that identifies the highest priority, active, multiplexed interrupt source. when epaipv is read, the epa interrupt pending bit associated with the epaipv priority value is cleared. 7 0 comp0 ? comp1 ? ovrtm1 ovrtm2 bit number function 7:4 reserved; always write as zeros. 3:0 ? any set bit indicates that the corresponding epa x interrupt source is pending. the bit is cleared when the epa interrupt priority vector register (epaipv) is read. ? 87c196la, lb only; reserved on 83c196ld. figure 7-6. epa interrupt pending 1 (epa_pend1) register 8xc196l x supplement 7-6 7.1.3 epa interrupt priority vector register figure 7-7 illustrates the epa interrupt priority vector (epaipv) register for the 8xc196l x mi- crocontroller family. epaipv address: reset state: 1fa8h 00h when an epa x interrupt occurs, the epa interrupt priority vector (epaipv) register contains a number that identifies the highest priority, active, multiplexed interrupt source (see table 7-2). epaipv allows software to branch via the tijmp instruction to the correct interrupt service routine when epa x is activated. reading epaipv clears the epa pending bit for the interrupt associated with the value in epaipv. when all the epa pending bits are cleared, the epa x pending bit is also cleared. 7 0 pv4 pv3 pv2 pv1 pv0 bit number bit mnemonic function 5:7 reserved; for compatibility with future devices, write zeros to these bits. 4:0 pv4:0 priority vector these bits contain a number from 01h to 14h corresponding to the highest-priority active interrupt source. this value, when used with the tijmp instruction, allows software to branch to the correct interrupt service routine. figure 7-7. epa interrupt priority vector register (epaipv) table 7-2. epa interrupt priority vectors value interrupt value interrupt value interrupt 14h 0dh ovr1 06h ovr8 13h 0ch ovr2 05h ovr9 12h epa6 0bh ovr3 04h comp0 ? 11h epa7 0ah 03h comp1 ? 10h epa8 09h 02h ovrtm1 0fh epa9 08h 01h ovrtm2 0eh ovr0 07h 00h none ? 87c196la, lb only; reserved on 83c196ld. 8 j1850 communications controller 8-1 chapter 8 j1850 communications controller the j1850 communications controller manages communications between multiple network nodes. this integrated peripheral supports the 10.4 kb/s vpw (variable pulse width) medium- speed class b in-vehicle network protocol. it also supports both the standard and in-frame re- sponse (ifr) message framing as specified by the society of automotive engineering ( sae) j1850 (revised may 1994) technical standards. its lower cost per node makes it suitable for diag- nostics and non-real-time data sharing in applications with high numbers of nodes. this chapter details the integrated j1850 controller and explains how to configure it. 8.1 j1850 functional overview the integrated j1850 communications controller transfers messages between network nodes ac- cording to the j1850 protocol. the complete j1850 communications protocol solution includes an on-chip, j1850 digital-logic controller working with an external analog bus transceiver circuit. figure 8-1 illustrates the j1850 protocol with the j1850 controller integrated on the 87c196lb 16-bit microcontroller and a standalone j1850 bus transceiver device. the example uses the har- ris hip7020 as the remote transceiver device. figure 8-1. integrated j1850 communications protocol solution the benefit of an integrated, j1850 protocol solution is threefold: ? minimizes cpu overhead for reception and transmission of j1850 messages. ? frees up serial and parallel communications ports for other purposes. ? offers significant printed-circuit board area savings when compared with conventional standalone protocol devices. a5168-01 87c196lb microcontroller pll/ clkout clock txj1850 rxj1850 tx rx hip7020 j1850 bus 8xc196l x supplement 8-2 the j1850 controller can handle network protocol functions including message frame sequenc- ing, bit arbitration, in-frame response (ifr) messaging, error detection, and delay compensation. the j1850 communications controller (figure 8-2) consists of a control state machine (csm), symbol synchronization and timing (sst) circuitry, six control and status registers, transmit and receive buffers, and an interrupt handler. figure 8-2. j1850 communications controller block diagram a5169-01 peripheral data bus j_cfg j_cmd j_rx jrx_buf jtx_buf j_tx j_stat j_dly interrupt handler j1850st j1850rx j1850tx ovr undr tx rx bus error error detection circuitry bit arbitration circuitry cyclic redundancy check circuitry csm symbol encoder symbol decoder prescaler delay compensator sst digital filter internal clocking txj1850 rxj1850 j1850 communications controller 8-3 j1850 communications controller 8.2 j1850 controller signals and registers table 8-1 describes the j1850 controllers pins, and table 8-2 describes the control and status registers. table 8-1. j1850 controller signals signal type description rxj1850 i receive carries digital symbols from a remote transceiver to the j1850 controller. txj1850 o transmit carries digital symbols from the j1850 controller to a remote transceiver. table 8-2. control and status registers mnemonic address description j_cfg 1f54h j1850 configuration program this byte register to specify the oscillator prescaler divisor, mode of operation, and normalization bit format. you must write to this register during the initialization sequence. j_cmd 1f51h j1850 command program this byte register to specify the number of bytes to be transmitted in the next message frame. this register also monitors the status of the message transmission in progress, and it can abort, ignore, or retry a message if necessary. read this register to determine the status of transmissions in progress. j_dly 1f58h j1850 delay compensation program this byte register to define the length of the delay time through the external transceiver to compensate for the inherent propagation delays and to accurately resolve bus contention during arbitration. you must write to this register during the initialization sequence. j_rx 1f52h j1850 receiver read this byte register to receive data in byte increments from the j1850 bus to the microcontroller cpu. this register is buffered to allow for reception of a second data byte while the first data byte is being read. j_stat 1f53h j1850 status read this byte register to determine the current status of the receive and transmit buffers and the j1850 interrupt sources. you can also determine bus status and in-frame response messaging status. all bits of this register are cleared when read, with the exception of the bus_stat bit. j_tx 1f50h j1850 transmitter program this byte register to transmit data in byte increments to the j1850 bus from the microcontroller cpu. this register is buffered to allow for writing of a second data byte while the first data byte is being shifted out. 8xc196l x supplement 8-4 8.3 j1850 controller operation this section describes the control state machine (which contains the cyclic redundancy check generator) and the symbol synchronization and timing circuitry for j1850 transmissions and re- ceptions. 8.3.1 control state machine the control state machine (csm) represents the engine of the digital circuitry portion of the j1850 communications controller. the csm handles all message framing for standard and in- frame response (ifr) messaging, data validation, bus contention, bit arbitration, and error detec- tion. 8.3.1.1 cyclic redundancy check generator the cyclic redundancy check (crc) generator circuitry calculates and checks the crc byte gen- erated for both transmitted and received standard messages as specified by sae j1850 protocol specification for class b in-vehicle networks. the crc calculation is a code byte of information that verifies the proper reception or transmission of your message. the calculated crc code byte is always appended as the last byte of your transmitted message. on reception, the calculated crc checksum byte always results in a value of c4h for valid messages. an invalid crc check- sum during reception signals the presence of an error in your incoming message, which immedi- ately sets the j1850 bus error (j1850be) bit in the j_stat register (figure 8-19 on page 8-21). int_mask 0008h interrupt mask bits 6 and 7 in this register enable and disable the j1850 receive and transmit interrupt requests, respectively. int_mask1 0013h interrupt mask 1 bit 0 in this register enables and disables the j1850 bus error interrupt request. int_pend 0009h interrupt pending bits 6 and 7 in this register, when set, indicate pending j1850 receive and transmit interrupt requests, respectively. int_pend1 0012h interrupt pending 1 bit 0 in this register, when set, indicates a pending j1850 bus error interrupt request. ptssel 0004h pts select bits 6, 7, and 8 of this word register select either a pts service request or a standard interrupt service request for j1850tx, j1850rx, and j1850st interrupts, respectively. ptssrv 0006h pts service bits 6, 7, and 8 of this word register are set by hardware to request an end-of-pts interrupt for the j1850. table 8-2. control and status registers (continued) mnemonic address description 8-5 j1850 communications controller 8.3.1.2 bus contention bus contention arises when multiple nodes attempt to access and transmit message frames across the j1850 bus simultaneously. this creates a conflict on the bus. the recognition of conflicting symbols or bits on the bus is referred to as contention detection . for example, if a node observes a difference between a symbol it transmits to the j1850 bus and the symbol that it detects on the bus, that node has detected contention to the transmission of its message frame. only one message frame from one node vying for the bus wins arbitration on each symbol or bit of its frame. this winning message frame does not experience or detect contention. the message frames that were not awarded arbitration will experience contention. 8.3.1.3 bit arbitration a bit arbitration scheme is used to resolve such conflicts as bus contention. the j1850 protocol uses the carrier sense multiple access (csma) bit arbitration scheme. bit arbitration is the pro- cess of settling conflicts that occur when multiple nodes attempt to transmit one bit or symbol at a time across a single bus. a symbol is simply a timing-level formatted bit. by definition, a node that detects contention has lost arbitration and will discontinue transmitting any further symbols remaining in its message frame. remaining nodes vying for the bus will continue to send their symbols until the next instance of contention is detected or arbitration is awarded. this process continues until a complete message frame from one node has been transmitted. for details on this arbitration scheme, refer to the bit arbitration example on page 8-7. 8.3.1.4 error detection the j1850 controllers error detection logic monitors the bus for four error conditions, and sets the j1850be interrupt pending bit in the j_stat register if an error occurs. the following list describes each error type: ? crc error the calculated crc checksum received on incoming messages has a value other than c4h (the expected value for all received message frames). ? bus symbol timing error the symbol stream on the j1850 bus contains an invalid symbol. an invalid symbol is any signal that is between 8 s and 34 s in duration. ? incomplete byte error an eod/eof symbol occurred,but was not on a byte boundary; the number of bits recieved was not a multiple of eight. ? no echo the message is transmitted; however, the transmissions echo back through the feedback loop to the receiver has not been detected within the allowable 60 s window. 8.3.2 symbol synchronization and timing circuitry the symbol synchronization and timing (sst) circuitry consists of a clock prescaler, digital filter, delay compensation circuitry, and synchronization and symbol encoding/decoding circuitry. the sst supports huntzicker encoding of symbols, which entails 10.4 kb/s variable pulse-width (vpw) operation for valid edge detection on message receptions. 8xc196l x supplement 8-6 8.3.2.1 clock prescaler because the 87c196lb microcontroller can operate at a variety of input frequencies (f xtal 1 ), the clock prescaler circuitry is used to provide a single, internal clock frequency (f/2) to ensure that the j1850 peripheral is clocked at the proper operating frequency. this is accomplished through the programmable clock prescaler bits, pre1:0 in the j_cfg register (figure 8-17 on page 8-18). the prescale bits support input frequencies of 8, 12, 16, and 20 mhz on the xtal1 pin. with the phase-locked loop (pll) circuitry enabled, the prescale bits can support input frequencies of 4, 6, 8, and 10 mhz on the xtal1 pin. table 8-3 details the relationships between the input frequency, the configuration of pll, the in- ternal clock frequency, and the prescaler bits. 8.3.2.2 digital filter to automatically reject noise spikes of 8 s or less in duration, the j1850 controller uses a digital filter between the rxj1850 input pin and the symbol synchronization logic. a noise spike is defined as an active or passive state pulse that is shorter in duration than a valid receive symbol at that state. a valid receive symbol is at least 34 s in duration. any symbol cap- tured on the bus between 8 s and 34 s in duration is considered invalid and is flagged by the j_stat register as a bus-symbol timing error. 8.3.2.3 delay compensation because the digital portion of the j1850 protocol is integrated onto the microcontroller and phys- ically separated from the transceiver and j1850 bus, control over critical timing parameters of various manufacturers remote transceivers is required. the delay compensation circuitry ad- dresses this requirement by providing the flexibility to compensate for propagation delay and pulse-width variations among various transceivers. the compensation circuitry synchronizes it- self to the leading edge of each input symbol, which allows for accurate detection of bus conten- tion during bit arbitration. the delay compensation is programmable through the j_dly register (figure 8-18 on page 8-20). 8.3.2.4 symbol encoding and decoding the j1850 protocol supports the huntzicker encoding method, which is based on variable pulse- width (vpw) bus modulation. vpw modulation is a forced high/low symbol transition formatting scheme that tracks the duration between two consecutive transitions and the level of the bus, ac- tive or passive (figure 8-3). table 8-3. relationships between input frequency, pll, and prescaler bits f xtal 1 internal clock frequency (f/2) pre1 pre0 pll disabled pll enabled 8 mhz 4 mhz 4 mhz 0 0 12 mhz 6 mhz 6 mhz 0 1 16 mhz 8 mhz 8 mhz 1 0 20 mhz 10 mhz 10 mhz 1 1 8-7 j1850 communications controller figure 8-3. huntzicker symbol definition for j1850 a symbol is defined as a timing-level formatted bit. the vpw symbol timing requirements stip- ulate that there is one symbol per transition and one transition per symbol. this ensures that a message frame will always result in a uniform square waveform of varying level durations. fig- ure 8-4 depicts a typical huntzicker formatted data byte of hex value cch. figure 8-4. typical vpw waveform bits 7 and 3 carry logic level 1 data; however, they are represented by a passive-level symbol in keeping with the vpw requirements. bits 4 and 0 carry logic level 0 data and are represented by an active-level symbol. 8.3.3 bit arbitration example the drive capacity of each symbol establishes the priority for arbitration. by definition, an active bus level is a driven state, and a passive bus level is a non-driven, or idle, state. a driven bus state is always given priority over an idle bus in arbitration. an active 0 state has priority over an active 1 state in arbitration, because the active 0 state is driven over a longer duration, 128 s versus the active 1 states drive time of 64 s. similarly, a passive 0 state has priority over a passive 1 state, because the passive 0 state comes out of its idle state in a shorter period of time, 64 s versus the passive 1 states idle time of 128 s. for example, figure 8-5 illustrates four nodes vying for the bus. node b is the first node to dis- continue transmitting when it attempts to transmit a passive 1 symbol onto the bus. at the point a5219-01 0 1 "active 0" 128s 0 1 or "passive 0" 64s 0 1 "active 1" 64s 0 1 or "passive 1" 128s a5222-01 b7 "1" b6 "1" b5 "0" b4 b3 "1" "0" b0 "0" b1 "0" b2 "1" 8xc196l x supplement 8-8 of arbitration, nodes a, c, and d are all transmitting an active 0 symbol, thus the idle state of the passive 1 symbol is overruled in favor of the driven state of the active 0 symbol. node c is the next node to discontinue transmitting when it attempts to take control of the bus by transmitting an active 1 symbol. however, nodes a and d maintain control by continuing to drive the bus with an active 0 symbol. finally, node d discontinues transmitting when its attempt to hold the bus in an idle state is over- ruled by the driven state of the active 1 symbol on node a. thus, node a is awarded arbitration. the busline signal, detected on the bus by the receiver, reflects node as message, as this is the only node that did not experience contention. figure 8-5. bit arbitration example 8.4 message frames a message transmission or reception is transferred within a message frame that adds control and error-detection bits to the content of the message. the frame for an ifr message differs slightly from that for a standard message, but they contain similar information (figure 8-6). a5223-01 node b "0" "0" "0" "1" "0" "1" node c "0" "0" "0" "1" "0" "1" "0" node d busline "0" "0" "0" "0" "0" "1" "0" "1" "0" "0" node a point of arbitration "1" point of arbitration point of arbitration 8-9 j1850 communications controller figure 8-6. j1850 message frames a standard message frame is initiated by the responder and contains no more than 11 data bytes to be transmitted. an ifr message is a request initiating the recipient(s) to respond by transmit- ting data within the same frame. the following subsections describe each of the messaging forms. 8.4.1 standard messaging a standard message frame can best be described as a send mode only format that is initiated by the responder either to request information or to reply to a received message from a remote node. in addition to the actual data that is being transmitted, the standard message is composed of a header (1C3 bytes), a crc byte, and a series of start and end symbols. 8.4.1.1 header the header provides general information on the physical network and the necessary interface re- quirements. for a complete description of the header, refer to the society of automotive engineer- ing ( sae) j1850 specifications (revised may 1994). 8.4.1.2 crc byte the crc byte, calculated through the cyclic redundancy check generator, is a checksum value that verifies the accuracy of the data message transmitted onto the bus. the crc byte is appended to all data messages and optionally appended to ifr response messages. upon reception, the crc byte is compared with the value c4h. if the values match, the transmitted message is valid; otherwise, it is invalid, and an error flag in the j_stat register is set. 8.4.1.3 normalization bit the normalization bit (nb), found only in ifr messaging, defines the start of the ifr message response data. the nb is triggered by bit j_cmd.6 and is transmitted after an end-of-data (eod) symbol is detected on the bus. the timing format of the nb is assigned by the j_cfg register a5225-01 s o f i f s 1 byte crc e o f e o d 1-3 bytes header 1-11 bytes data ? standard frame 0-1 byte crc e o d s o f e o f i f s the number of data bytes to be transferred is unspecified if 0eh is written to j_cmd3:0. 1-32 bytes ifr data 1 byte crc e o d n b 1-3 bytes header 1-11 bytes data ? in-frame response (ifr) frame ? 8xc196l x supplement 8-10 (j_cfg.7) and considers whether the ifr message response has a crc byte appended. figure 8-7 depicts the sae preferred, active-level state bit format timing for the nb. figure 8-7. huntzicker symbol definition for the normalization bit 8.4.1.4 start and end message frame symbols five symbols are used to mark the start and end of a message frame and to allow the j1850 bus to properly recognize the interruption of a message transmission or reception. figure 8-8 illus- trates the formats and their respective timing. the following is a description of each symbol: ? start of frame (sof) this symbol signals the start of a message frame. this is an active- level state symbol only and appears once per frame. ? end of data (eod) this symbol signals the end of the data transmission. this is a passive- level state symbol only. it appears twice in ifr messaging: at the end of the initial request data field and at the end of the ifr data field. ? end of frame (eof) this symbol signals the end of a message frame and returns the bus to an idle state. this is a passive-level state symbol only. it appears once per frame. ? in-frame separation (ifs) the timing of this symbol allows for proper synchronization of multiple nodes during back-to-back transmissions. nodes contending for the bus must comply with one of two conditions before transmitting: wait for the ifs minimum timing to expire wait for a rising edge on the bus after the eof minimum timing has expired ? break (brk) this symbol signals an interruption during a bus transmission. at the point of termination, all nodes are reset. this is an active-level state symbol. a5220-01 0 1 nb for ifr with crc 128s 0 1 or nb for ifr without crc 64s 8-11 j1850 communications controller figure 8-8. definition for start and end of frame symbols table 8-4 details the symbol timing characteristics supported by the 87c196lb. table 8-4. huntzicker symbol timing characteristics name symbol bus level t tx min t tx nom t tx max t rx min t rx max units logic level 0 0 passive 60 64 68 34 <96 s active 122 128 134 96 <163 s logic level 1 1 passive 122 128 134 96 <163 s active 60 64 68 34 <96 s start of frame sof active 193 200 207 163 <239 s end of data eod passive 193 200 207 163 <239 s end of frame eof passive 271 280 289 239 <300 s in-frame separation ifs passive >300 >300 s break brk active 768 >239 s note: timings are based on the standard bus rate of 10.4 kb/s. when operating in 4x mode, the bus rate becomes 41.6 kb/s and all symbol timings are one fourth that shown. a5221-01 0 1 0 1 "break signal (brk)" "in-frame separation (ifs)" 300s+ 0 1 200s 0 1 "end of frame (eof)" 280s 0 1 768s+ 200s "start of frame (sof)" "end of data (eod)" 8xc196l x supplement 8-12 8.4.2 in-frame response messaging there are three types of in-frame response (ifr) message framings: type 1 (a single byte from a single responder), type 2 (a single byte from multiple responders), and type 3 (multiple bytes from a single responder). like the standard message frame, the ifr frame is composed of header, data, and crc bytes, and a series of start and end symbols. unlike the standard message frame, the actual length of the ifr message frame will differ based on the desired response. consider the following example: a systems controller (the requestor) requests an information up- date from each of four nodes (the responders) in the system. with type 1 messaging, the controller can receive a limited information update if it sends out four separate transmissions. with type 2 messaging, the controller can receive a limited information update by sending one message. with type 3 messaging, the controller can receive unlimited information; however, it will require four separate transmissions. the following subsections detail this example for the three ifr messag- ing types. 8.4.2.1 ifr messaging type 1: single byte, single responder no ifr messaging type carries a distinct advantage or disadvantage over the other messaging types. ifr messaging type 1 (figure 8-9) is ideal for use when requesting small amounts of in- formation from a single source in your system. in the above example, suppose you want to know how many pounds of pressure each of the four remote node sites experienced after the controller sent out a request to each node sensor to exert a given amount of pressure. if you use type 1 mes- saging, the controller will send four separate serial messages to the remote node sites in the sys- tem and wait for their responses. keeping the data timing a constant, the cpu overhead of transmitting these messages alone amounts to a minimum of 4.96 ms (refer to table 8-4 on page 8-11 for all symbol timings). figure 8-9. ifr type 1 message frame 8.4.2.2 ifr messaging type 2: single byte, multiple responders when response time is the highest consideration, ifr messaging type 2 is desirable. ifr type 2 messaging can monitor up to 32 remote nodes on a given request (see figure 8-10). while it al- lows only one byte of information per response, in many cases a single byte of information is more than adequate. in our example, suppose that each node sensor detected a pressure of 75 p.s.i. (pounds per square inch). the response (the value 75) would take a single byte, 46h, to communicate the reply. the maximum overhead required is 1.24 ms, or one fourth the time it would take type 1 messaging to achieve the same results. a5229-01 0-1 byte crc e o d s o f e o f i f s the number of data bytes to be transferred is unspecified if 0eh is written to j_cmd3:0. 1byte ifr data 1 byte crc e o d n b 1-3 bytes header 1-11 bytes data ? in-frame response (ifr) frame ? 8-13 j1850 communications controller figure 8-10. ifr type 2 message frame 8.4.2.3 ifr messaging type 3: multiple bytes, single responder ifr messaging type 3 (figure 8-11) is ideal for requesting large amounts of information from a single source in your system. you can compile up to 12 bytes of data from a remote node on a single request. in our example, for the same amount of cpu overhead as ifr type 1 messaging exhausted (4.96 ms), you can gather up to twelve times as much information. figure 8-11. ifr type 3 message frame 8.5 transmitting and receiving messages the j1850 controller can transmit and receive messages in either standard or ifr form. 8.5.1 transmitting messages to transmit a standard message, prepare the message in register ram and then write it to the j1850 transmit (j_tx) register (figure 8-12) one byte at a time. a5227-01 0-1 byte crc e o d s o f e o f i f s the number of data bytes to be transferred is unspecified if 0eh is written to j_cmd3:0. each d x block in the ifr data field represents a byte of data from a different remote node. 1 byte crc e o d n b 1-3 bytes header 1-11 bytes data ? ifr data field ?? in-frame response (ifr) frame ?? ? d 31 . . . . . . . . . . d 1 d 0 a5228-01 0-1 byte crc e o d s o f e o f i f s the number of data bytes to be transferred is unspecified if 0eh is written to j_cmd3:0. 1-12 bytes ifr data 1 byte crc e o d n b 1-3 bytes header 1-11 bytes data ? in-frame response (ifr) frame ? 8xc196l x supplement 8-14 transmitting the message requires that you first program the j1850 command (j_cmd) register to specify the number of bytes you want to transfer across the j1850 bus. the number of bytes specified must include the header byte(s). after the start of frame (sof) symbol is put on the bus, the first header byte is transferred to j_tx for transmission. this byte will automatically be trans- ferred into the j1850 transmit buffer (jtx_buf) and the second byte of the message frame will be written to j_tx. the transfer of the first byte to jtx_buf triggers the transmission process and generates the j1850 transmission (j1850tx) interrupt (if it is enabled), signaling that j_tx is available for another byte (figure 8-13). figure 8-13. j1850 transmit message structure after the byte in jtx_buf is transmitted, the byte residing in j_tx is automatically shifted into jtx_buf, freeing j_tx for another byte. this process continues until the csm has resolved the number of message bytes (msg3:0) programmed into the j_cmd register. if the last message byte being transmitted is shifted out before the msg x count expires, a j1850st core interrupt is generated and the ovr_undr (j_stat.3) bit records a transmitter underflow error in the j_stat register. j_tx address: reset state: 1f50h 00h the j1850 transmitter (j_tx) register transfers data in byte increments to the j1850 bus from the microcontroller cpu. this register is buffered to allow for transmission of a second data byte while the first data byte is being shifted out. this byte register can be read or written, and is addressable through windowing . 7 0 transmit byte bit number bit mnemonic function 7:0 db7:0 data bits these eight bits compose the data byte to be transmitted to the j1850 bus. figure 8-12. j1850 transmitter (j_tx) register a5235-01 cpu jtx_buf j_tx message transmit interrupt (j1850tx) set j1850 bus 8-15 j1850 communications controller note an overrun condition can occur on transmission if the transmit buffer, jtx_buf, is overwritten. 8.5.2 receiving messages for a message reception, after a sof is detected on the bus, the controller starts to shift data sym- bols into the j1850 receive buffer (jrx_buf) until an entire data byte has been received. this byte is automatically transferred into the j1850 receive (j_rx) register (figure 8-14) and the sub- sequent byte is written into the empty jrx_buf. the transfer of the first byte to j_rx triggers the reception process and generates the j1850 re- ception (j1850rx) interrupt (if it is enabled), signaling that jrx_buf is available for another byte (figure 8-15). figure 8-15. j1850 receive message structure after j_rx is read, the byte residing in jrx_buf is automatically shifted into j_rx, freeing jrx_buf for another reception. this process continues until an end of data (eod) symbol is en- countered. j_rx address: reset state: 1f52h 00h the j1850 receiver (j_rx) register transfers received data in byte increments from the j1850 bus to the microcontroller cpu. this register is buffered to allow for reception of a second data byte while the first data byte is being read. this byte register can be read or written, and is addressable through windowing . 7 0 receive byte bit number bit mnemonic function 7:0 db7:0 data bits these eight bits compose the last data byte received from the j1850 bus. figure 8-14. j1850 receiver (j_rx) register a5236-01 cpu j_rx jrx_buf message receive interrupt (j1850rx) set j1850 bus 8xc196l x supplement 8-16 if a third byte is received before j_rx is read, a j1850st core interrupt is generated and the ovr_undr (j_stat.3) bit records a receiver overrun error in the j_stat register. 8.5.3 ifr messages in-frame response (ifr) messaging is identical in setup to standard messaging for both transmis- sion and reception. it uses the same registers to configure, communicate, and control data. the difference is that the requestor initiating the ifr message sequence writes the message specifying a response from either one or more nodes in the system. framing a message in this manner by- passes needless cpu overhead that can result from lengthy eof symbols, and it gives you a faster response to the information you are accessing from remote sites in your system. (refer to in- frame response messaging on page 8-12 for a detailed explanation). 8.6 programming the j1850 controller this section explains how to configure the j1850 controller. several registers combine to control the configuration: the command register, the configuration register, the delay compensation reg- ister, and the status register. programming the j1850 controller requires that you first program the configuration and delay registers during initialization. you need to program these two registers only once per initializa- tion sequence. after initialization, you must first program the command register, followed by either the receive or transmit register, and then the status register. 8.6.1 programming the j1850 command (j_cmd) register the j1850 command register (figure 8-16) determines the messaging type, specifies the number of bytes to be transmitted in the next message frame, and updates the status of the message trans- mission in progress. 8-17 j1850 communications controller j_cmd address: reset state: 1f51h 00h the j1850 command (j_cmd) register determines the messaging type, specifies the number of bytes to be transmitted in the next message frame, and updates the status of the message transmission in progress. this byte register can be directly addressed through windowing . you must write to this register prior to transmitting every message. 7 0 auto ifr ignore abort msg3 msg2 msg1 msg0 bit number bit mnemonic function 7 auto automatic transmit retry this bit, when arbitration is lost on the first byte of your message, prompts the transmitter to automatically retry until the byte is successfully transmitted. automatic retry applies only to the first byte. 0 = normal operation 1 = enable automatic retry 6 ifr in-frame response indicator this bit signals that a normalization bit (nb) is to be sent after an end-of- data symbol is detected on the bus and that the subsequent byte written to the j1850 transmitter (j_tx) register is an in-frame response (ifr). 0 = standard messaging 1 = next byte written to j_tx is an ifr 5 ignore ignore incoming message this bit instructs the bus to ignore the incoming message until an eof symbol is detected. the bit is cleared after an eof symbol is detected. 0 = normal operation 1 = ignore incoming message 4 abort abort transmission this bit aborts any transmission in progress and flushes the transmit buffer (jtx_buf). to prevent another node from mistakenly assuming that the last byte was a crc byte, two extra 1s are appended. 0 = normal operation 1 = abort transmission in progress 3:0 msg3:0 message these four bits specify the number of bytes to be transmitted in the next message frame. this number includes the header, but not the crc byte. in normal messaging, the maximum number of bytes you can transmit in a message frame is eleven. msg3:0 operation purpose fh termination byte terminate block transmission eh block transmission transmit unspecified number of bytes dh reserved ch reserved b:0h normal messaging transmit specified number of bytes figure 8-16. j1850 command (j_cmd) register 8xc196l x supplement 8-18 8.6.2 programming the j1850 configuration (j_cfg) register the j1850 configuration register (figure 8-17) selects the proper oscillator prescaler, initiates a transmission break for debugging, invokes clock quadrupling operation, and selects the normal- ization bit format. j_cfg address: reset state: 1f54h 00h the j1850 configuration (j_cfg) register selects the proper oscilator prescaler, initiates transmission break for debug, invokes clock quadrupling operation, and selects the normalizartion bit format. this byte register can be directly addressed through windowing . all j1850 bus activity is ignored until you first write to this register. 7 0 nbf ifr3 4xm txbrk rxpol pre1 pre0 bit number bit mnemonic function 7 nbf normalization bit format this bit specifies which normalization bit (nb) format is to be used. ifr with crc byte ifr without crc byte 0 = active long nb 0 = active short nb 1 = active short nb 1 = active long nb 6 ifr3 type 3 ifr messaging this bit selects type 3 ifr messaging, which supports the in-frame transfer of an unspecified number of data bytes. 0 = normal operation 1 = type 3 ifr messaging 5 4xm oscillator quadruple (4x) mode this bit allows the j1850 peripheral to operate at four times the normal bit transfer rate (41.6 kb/s versus 10.4 kb/s). 0 = normal operation 1 = 4x mode operation 4 txbrk transmission break this bit will terminate any transmission in progress by writing a break (brk) symbol to the bus. 0 = normal operation 1 = transmit brk symbol onto bus 3 rxpol receive polarity this bit changes the polarity of the receive symbol. 0 = normal operation C rx input inverted 1 = receive polarity enabled C rx input non-inverted figure 8-17. j1850 configuration (j_cfg) register 8-19 j1850 communications controller 8.6.3 programming the j1850 delay compensation (j_dly) register the j1850 delay compensation register (figure 8-18) allows you to program the necessary delay time through the external transceiver to compensate for the inherent propagation delays and to accurately resolve bus contention during arbitration. 2 reserved; for compatibility with future devices, write zero to this bit. 1:0 pre1:0 j1850 oscillator prescaler these bits ensure proper operation of the j1850 peripheral at the supported input frequencies (f xtal 1 ). pre1 pre0 f xtal 1 00 8 mhz 0 1 12 mhz 1 0 16 mhz 1 1 20 mhz j_cfg address: reset state: 1f54h 00h the j1850 configuration (j_cfg) register selects the proper oscilator prescaler, initiates transmission break for debug, invokes clock quadrupling operation, and selects the normalizartion bit format. this byte register can be directly addressed through windowing . all j1850 bus activity is ignored until you first write to this register. 7 0 nbf ifr3 4xm txbrk rxpol pre1 pre0 bit number bit mnemonic function figure 8-17. j1850 configuration (j_cfg) register (continued) 8xc196l x supplement 8-20 j_dly address: reset state: 1f58h 00h the j1850 delay (j_dly) register allows you compensate for the inherent propagation delays and to accurately resolve bus contention during arbitration. this byte register can be directly addressed through windowing . 7 0 dly4 dly3 dly2 dly1 dly0 bit number bit mnemonic function 7:5 reserved; for compatibility with future devices, write zeros to these bits. 4:0 dly4:0 delay time these five bits specify the desired propagation delay between the j1850 controller circuitry and the off-chip transceiver device, in units of microseconds (s). figure 8-18. j1850 delay (j_dly) register 8-21 j1850 communications controller 8.6.4 programming the j1850 status (j_stat) register the j1850 status register (figure 8-19) provides the current status of the message and the four interrupt sources associated with the j1850 protocol. j_stat address: reset state: 1f53h 00h the j1850 status (j_stat) register provides the current status of the message transfer, the receive and transmit buffers, and the four interrupt sources associated with the j1850 protocol. this byte register can be directly addressed through windowing . you must write to this register before transmitting each message. reading this register clears all bits except bus_stat. 7 0 ifr_rcv bus_cont bus_stat brk_rcv ovr_undr msg_tx msg_rx j1850be bit number bit mnemonic function 7 ifr_rcv in-frame response received this bit indicates whether the ifr byte has been received and is ready to be read from the j1850 receiver (j_rx) register. 0 = no action 1 = ifr byte received 6 bus_cont j1850 bus contention this bit indicates whether bus contention has been detected and arbitration has been lost. 0 = no action 1 = bus contention 5 bus_stat j1850 bus status this bit indicates whether a transmission or reception is in progress on the j1850 bus. 0 = j1850 bus idle 1 = j1850 bus busy 4 brk_rcv break received this bit indicates whether a brk symbol has been detected on the j1850 bus. 0 = no action 1 = brk symbol detected 3 ovr_undr receive overrun/transmit underflow interrupt this bit indicates whether a receive buffer overrun (ovr) or transmit buffer underflow (undr) has occurred. an overrun occurs when a symbol is received while both j_rx and jrx_buf contain unread bytes. an underflow occurs when a transmission is attempted while both j_tx and jtx_buf are empty. 0 = normal operation 1 = ovr or undr detected figure 8-19. j1850 status (j_stat) register 8xc196l x supplement 8-22 2 msg_tx message transmit interrupt this bit signals the successful transmission of a message upon detecting the eod symbol. 0 = no action 1 = message transmitted 1 msg_rx message receive interrupt this bit signals the successful reception of a message upon detecting the eod symbol. 0 = no action 1 = message received 0 j1850be j1850 bus error interrupt this bit is set if one or more of the following conditions occur: ? the calculated crc for a received message does not equal c4h ? an incomplete byte is received on the bus ? an invalid bus symbol is detected on the bus ? a transmission occurs and the feedback through the receiver is not detected within 60 s j_stat address: reset state: 1f53h 00h the j1850 status (j_stat) register provides the current status of the message transfer, the receive and transmit buffers, and the four interrupt sources associated with the j1850 protocol. this byte register can be directly addressed through windowing . you must write to this register before transmitting each message. reading this register clears all bits except bus_stat. 7 0 ifr_rcv bus_cont bus_stat brk_rcv ovr_undr msg_tx msg_rx j1850be bit number bit mnemonic function figure 8-19. j1850 status (j_stat) register (continued) 9 minimum hardware considerations 9-1 chapter 9 minimum hardware considerations this chapter discusses the major hardware consideration differences between the 8xc196l x and the 8xc196k x . the 8xc196l x has implemented a reset source sfr that reveals the source of the most recent reset request. 9.1 identifying the reset source the reset source (rstsrc) register indicates the source of the last reset that the microcontroller encountered (figure 9-1). if more than one reset occurs at the same time, all of the corresponding rstsrc bits are set. reading this sfr clears all the register bits. rstsrc address: reset state: 1f92h xxh (1) the reset source (rstsrc) register indicates the source(s) of the last reset that the microcontroller encountered. 7 0 cfdrst wdtrst sfwrst extrst bit number bit mnemonic function 7:4 reserved; for compatibility with future devices, write zeros to these bits. 3 cfdrst clock failure detection reset when set, this bit indicates that a failed clock caused the last reset. 2 wdtrst watchdog timer reset when set, this bit indicates that the watchdog timer caused the last reset. 1 sfwrst software reset when set, this bit indicates that either the rst instruction or the idlpd instruction used with an illegal key caused the last reset. 0 extrst external reset when set, this bit indicates that the reset# pin being asserted caused the last reset. note: 1. the state of the rstsrc register is inderterminate on a v cc power up condition. all other reset states will have the corresponding reset event bit set in the register. figure 9-1. reset source (rstsrc) register 8xc196l x supplement 9-2 9.2 design considerations for 8xc196la, lb, and ld with the exception of a few new multiplexed functions, the 8xc196l x microcontrollers are pin compatible with the 8xc196j x microcontrollers. the 8xc196j x microcontrollers are 52-lead versions of 8xc196k x microcontrollers. follow these recommendations to help maintain hardware and software compatibility between the 8xc196l x , 8xc196k x , and future microcontrollers. ? bus width. since the 8xc196l x has neither a wrh# nor a buswidth pin, the microcontroller cannot dynamically switch between 8- and 16-bit bus widths. program the ccbs to select 8-bit bus mode. ? wait states. since the 8xc196l x has no ready pin, the microcontroller cannot rely on a ready signal to control wait states. program the ccbs to limit the number of wait states (0, 1, 2, or 3). ? epa6Cepa7. these functions exist in the 8xc196l x , but the associated pins are omitted. you can use these functions as software timers, to start a/d conversions (on 87c196la and lb only), or to reset the timers. ? slave port. since the 8xc196l x has no p5.1/slpcs and p5.4/slpint pins, you cannot use the slave port. ? once mode. on the 8xc196l x , the once mode entry function is multiplexed with p2.6 (and txj1850 on the 87c196lb) rather than with p5.4 as it is on the 8xc196k x (p5.4/slpint/once). ? nmi. since the 8xc196l x has no nmi pin, the nonmaskable interrupt is not supported. initialize the nmi vector (at location 203eh) to point to a ret instruction. this method provides glitch protection only. ? i/o ports. the following port pins do not exist in the 8xc196l x : p0.0Cp0.1, p1.4Cp1.7, p2.3 and p2.5, p5.1 and p5.4Cp5.7, p6.2 and p6.3. software can still read and write the associated p x _reg, p x _mode, and p x _dir registers. configure the registers for the omitted pins as follows: clear the corresponding p x _dir bits. (configures pins as complementary outputs.) clear the corresponding p x _mode bits. (selects i/o port function.) write either 0 or 1 to the corresponding p x _reg bits. (effectively ties signals low or high.) do not use the bits associated with the omitted port pins for conditional branch instructions. treat these bits as reserved. ? auto programming. during auto programming, the 8xc196l x supports only a 16-bit, zero-wait-state bus configuration. 10 special operating modes 10-1 chapter 10 special operating modes the 8xc196lxs idle and powerdown modes are the same as those of the 8xc196kx. however, the clock circuitry has changed, and the on-circuit emulation (once) special-purpose mode op- eration has changed slightly because of the new reset state pin levels that have been implemented. 10.1 internal timing the 87c196la and lb clock circuitry (figure 10-1) implements a phase-locked loop and clock multiplier circuitry, which can substantially increase the cpu clock rate while using a lower-fre- quency input clock. 8xc196l x supplement 10-2 figure 10-1. clock circuitry (87c196la, lb only) 10.2 entering and exiting once mode once mode isolates the device from other components in the system to allow printed-circuit- board testing or debugging with a clip-on emulator. during once mode, all pins except xtal1, xtal2, v ss , and v cc are weakly pulled either high or low. during once mode, reset# must be held high or the device will exit once mode and enter the reset state. on the 87c196la and lb, the reset state level of all 41 general-purpose i/o pins has changed from a weak logic 1 (wk1) to a weak logic 0 (wk0). once shares a package with port pin 2.6. asserting and holding the once signal high during the rising edge of reset# causes the device to enter once mode. to prevent accidental entry into once mode, configure this pin as phase-locked loop clock multiplier phase comparator filter phase-locked oscillator a5290-01 disable pll (powerdown) xtal1 xtal2 f xtal1 disable oscillator (powerdown) 0 1 disable clocks (idle, powerdown) 1 0 pllen 2f xtal1 clock generators programmable divider (clk1:0) disable clock input (powerdown) cpu clocks (ph1, ph2) peripheral clocks (ph1, ph2) disable clocks (powerdown) clkout f f/2 osc f xtal1 f/2 divide by two circuit clock failure detection to reset logic 10-3 special operating modes an output. if you choose to configure this pin as an input, always hold it low during reset and en- sure that your system meets the v ih specification to prevent inadvertent entry into once mode. 11 programming the nonvolatile memory 11-1 chapter 11 programming the nonvolatile memory the 87c196la and lb microcontrollers contain 24 kbytes (2000C7fffh) of one-time-pro- grammable read-only memory (otprom). otprom is similar to eprom, but it comes in a windowless package and cannot be erased. you have the option of programming the otprom yourself or having the factory program it as a quick-turn rom product (the latter option may not be available for all devices). note in this supplement, otprom refers to the devices internal read-only memory, whether it is eprom or otprom, and eprom refers specifically to eprom devices. the 87c196la and lb programming signals, registers, and procedures are the same as those of the 87c196k x . this chapter describes the differences in memory mapping and programming cir- cuits for the 87c196la and lb. 11.1 signature word and programming voltage values the 8xc196l x s programming voltage values are the same as those of the 8xc196k x ; however, the signature word value differs. table 11-1 lists the signature word and programming voltage values. 11.2 otprom address map the otprom contains customer-specified special-purpose and program memory (table 11-2). the 128-byte special-purpose address partition is used for interrupt vectors, the chip configura- tion bytes (ccbs), and the security key. several locations are reserved for testing or for use in future products. write the value (20h or ffh) indicated in table 11-2 to each reserved location. the remainder of the otprom is available for code storage. table 11-1. signature word and programming voltage values device signature word programming v cc programming v pp location value location value location value 87c196la 0070h 871bh 0072h 40h 0073h 0a0h 87c196lb 0070h 871bh 0072h 40h 0073h 0a0h 8xc196l x supplement 11-2 11.3 slave programming circuit and address map figure 11-1 shows the circuit diagram and table 11-3 details the address map for slave program- ming of the 87c196la and lb devices. table 11-2. 87c196la, lb otprom address map address range (hex) description 7fff 2080 program memory 207f 205e reserved (each location must contain ffh) 205d 2040 pts vectors 203f 2030 upper interrupt vectors 202f 2020 security key 201f 201c reserved (each location must contain ffh) 201b reserved (must contain 20h) 201a ccb1 2019 reserved (must contain 20h) 2018 ccb0 2017 2016 ofd flag for qrom or mrom codes ? 2015 2014 reserved (each location must contain ffh) 2013 2000 lower interrupt vectors ? intel manufacturing uses this location to determine whether to program the ofd bit. customers with quick-rom (qrom) or masked-rom (mrom) codes who desire oscillator failure detection should equate this location to the value 0cdeh. 11-3 programming the nonvolatile memory figure 11-1. slave programming circuit table 11-3. slave programming mode address map description address comments otprom 2000C7fffh otprom cells ofd 0778h otprom cell ded ? 0758h uprom cell dei ? 0718h uprom cell pccb 0218h test eprom programming v cc 0072h read only programming v pp 0073h read only signature word 0070h read only ? these bits program the uprom cells. once these bits are programmed, they cannot be erased, and dynamic failure analysis of the device is impossible. p2.6 p2.4 p2.2 p2.1 p2.0 p0.7/pmode.3 p0.6/pmode.2 p0.5/pmode.1 p0.4/pmode.0 angnd ea# xtal1 0.1 f reset# clock ea# pullups required p4.7 - p3.0 87c196la, lb reset# 10 k w v cc v cc v pp v cc a5277-01 v ref v cc v ss p3.7:0 p4.7:0 pbus v pp cpver ainc# prog# pale# pver 8xc196l x supplement 11-4 11.4 serial port programming circuit and address map figure 11-2 shows the circuit and table 11-4 details the address map for serial port programming. figure 11-2. serial port programming circuit 5 9 4 8 3 7 2 6 1 1.8k w 1.8k w 1.8k w 1.8k w 1.8k w 10f a5278-01 rxd txd rxd txd v cc 87c196la, lb 30 pf 30 pf xtal1 xtal2 p0.7/pmode.3 p0.6/pmode.2 p0.5/pmode.1 p0.4/pmode.0 angnd v ref v cc abc v cc v pp ea# 0.01 f v pp p2.0/txd p2.1/rxd 10 f v cc reset# 1n914 2n2222a 2n2907 1n914 11-5 programming the nonvolatile memory table 11-4. serial port programming mode address map description address range normal operation serial port programming mode internal otprom 2000C7fffh a000Cffffh external memory 4000C9fffh do not address 2400C3fffh test rom and rism 2000C23ffh a signal descriptions a-1 appendix a signal descriptions this appendix provides reference information for the pin functions of the 8xc196l x microcon- trollers. a.1 functional groupings of signals tables a-1, a-2, and a-3 list the signal assignments for the 8xc196l x microcontrollers, grouped by function. a diagram of each microcontroller shows the pin location of each signal. 8xc196l x supplement a-2 table a-1. 87c196la signals arranged by functional categories addr & data input/output (contd) program control processor control name pin name pin name pin name pin ad0 22 p2.1 / rxd 28 ainc# 30 ea# 24 ad1 21 p2.2 29 cpver 31 extint 29 ad2 20 p2.4 30 pact# 32 pllen 6 ad3 19 p2.6 31 pale# 28 reset# 23 ad4 18 p2.7 32 pbus.0 22 xtal1 52 ad5 17 p3.0 22 pbus.1 21 xtal2 51 ad6 16 p3.1 21 pbus.2 20 ad7 15 p3.2 20 pbus.3 19 bus cont & status ad8 14 p3.3 19 pbus.4 18 name pin ad9 13 p3.4 18 pbus.5 17 adv# / ale 2 ad10 12 p3.5 17 pbus.6 16 clkout 32 ad11 11 p3.6 16 pbus.7 15 rd# 5 ad12 10 p3.7 15 pbus.8 14 wr# / wrl# 6 ad13 9 p4.0 14 pbus.9 13 ad14 8 p4.1 13 pbus.10 12 power & ground ad15 7 p4.2 12 pbus.11 11 name pin p4.3 11 pbus.12 10 angnd 39 input/output p4.4 10 pbus.13 9 v cc 26 name pin p4.5 9 pbus.14 8 v pp 4 p0.2 / ach2 33 p4.6 8 pbus.15 7 v ref 40 p0.3 / ach3 34 p4.7 7 pmode.0 35 v ss 3 p0.4 / ach4 35 p5.0 2 pmode.1 36 v ss 1 1 p0.5 / ach5 36 p5.2 6 pmode.2 37 v ss 1 25 p0.6 / ach6 37 p5.3 5 pmode.3 38 p0.7 / ach7 38 p6.0 / epa8 / comp0 45 prog# 29 p1.0 / epa0 / t2clk 44 p6.1 / epa9 / comp1 46 pver 27 p1.1 / epa1 43 p6.4 / sc0 47 p1.2 / epa2 / t2dir 42 p6.5 / sd0 48 p1.3 / epa3 41 p6.6 / sc1 49 p2.0 / txd 27 p6.7 / sd1 50 a -3 signal descriptions fig u re a-1 . 87c 1 96 l a 52 - pin p l cc pac k ag e p6.1 / epa9 / comp1 p6.0 / epa8 / comp0 p1.0 / epa0 / t2clk p1.1 / epa1 p1.2 / epa2 / t2dir p1.3 / epa3 v ref angnd p0.7 / ach7 / pmode.3 p0.6 / ach6 / pmode.2 p0.5 / ach5 / pmode.1 p0.4 / ach4 / pmode.0 p0.3 / ach3 5 1 . s u b p / 7 . 4 p / 5 1 d a # l r w / # r w / n e l l p / 2 . 5 p # d r / 3 . 5 p v p p v s s e l a / # v d a / 0 . 5 p v 1 s s 1 l a t x 2 l a t x 1 d s / 7 . 6 p 1 c s / 6 . 6 p 0 d s / 5 . 6 p 0 c s / 4 . 6 p a3419-03 ad14 / p4.6 / pbus.14 ad13 / p4.5 / pbus.13 ad12 / p4.4 / pbus.12 ad11 / p4.3 / pbus.11 ad10 / p4.2 / pbus.10 ad9 / p4.1 / pbus.9 ad8 / p4.0 / pbus.8 ad7 / p3.7 / pbus.7 ad6 / p3.6 / pbus.6 ad5 / p3.5 / pbus.5 ad4 / p3.4 / pbus.4 ad3 / p3.3 / pbus.3 ad2 / p3.2 / pbus.2 46 45 44 43 42 41 40 39 38 37 36 35 34 xx87c196la20 view of component as mounted on pc board 8 9 10 11 12 13 14 15 16 17 18 19 20 1 . s u b p / 1 . 3 p / 1 d a 0 . s u b p / 0 . 3 p / 0 d a # t e s e r # a e v 1 s s v c c r e v p / d x t / 0 . 2 p # e l a p / d x r / 1 . 2 p # g o r p / t n i t x e / 2 . 2 p # c n i a / 4 . 2 p r e v p c / e c n o / 6 . 2 p # t c a p / t u o k l c / 7 . 2 p 2 h c a / 2 . 0 p 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 0 3 1 3 2 3 3 3 7 6 5 4 3 2 1 2 5 1 5 0 5 9 4 8 4 7 4 8xc196l x supplement a-4 table a-2. 87c196lb signals arranged by functional categories addr & data input/output (contd) program control processor control name pin name pin name pin name pin ad0 22 p2.1 / rxd 28 ainc# 30 ea# 24 ad1 21 p2.2 29 cpver 31 extint 29 ad2 20 p2.4 / rxj1850 30 pact# 32 pllen 6 ad3 19 p2.6 / txj1850 31 pale# 28 reset# 23 ad4 18 p2.7 32 pbus.0 22 xtal1 52 ad5 17 p3.0 22 pbus.1 21 xtal2 51 ad6 16 p3.1 21 pbus.2 20 ad7 15 p3.2 20 pbus.3 19 bus cont & status ad8 14 p3.3 19 pbus.4 18 name pin ad9 13 p3.4 18 pbus.5 17 adv# / ale 2 ad10 12 p3.5 17 pbus.6 16 clkout 32 ad11 11 p3.6 16 pbus.7 15 rd# 5 ad12 10 p3.7 15 pbus.8 14 wr# / wrl# 6 ad13 9 p4.0 14 pbus.9 13 ad14 8 p4.1 13 pbus.10 12 power & ground ad15 7 p4.2 12 pbus.11 11 name pin p4.3 11 pbus.12 10 angnd 39 input/output p4.4 10 pbus.13 9 v cc 26 name pin p4.5 9 pbus.14 8 v pp 4 p0.2 / ach2 33 p4.6 8 pbus.15 7 v ref 40 p0.3 / ach3 34 p4.7 7 pmode.0 35 v ss 3 p0.4 / ach4 35 p5.0 2 pmode.1 36 v ss 1 1 p0.5 / ach5 36 p5.2 6 pmode.2 37 v ss 1 25 p0.6 / ach6 37 p5.3 5 pmode.3 38 p0.7 / ach7 38 p6.0 / epa8 / comp0 45 prog# 29 p1.0 / epa0 / t2clk 44 p6.1 / epa9 / comp1 46 pver 27 p1.1 / epa1 43 p6.4 / sc0 47 p1.2 / epa2 / t2dir 42 p6.5 / sd0 48 p1.3 / epa3 41 p6.6 / sc1 49 p2.0 / txd 27 p6.7 / sd1 50 a -5 signal descriptions fig u re a-2 . 87c 1 96 l b 52 - pin p l cc pac k ag e p6.1 / epa9 / comp1 p6.0 / epa8 / comp0 p1.0 / epa0 / t2clk p1.1 / epa1 p1.2 / epa2 / t2dir p1.3 / epa3 v ref angnd p0.7 / ach7 / pmode.3 p0.6 / ach6 / pmode.2 p0.5 / ach5 / pmode.1 p0.4 / ach4 / pmode.0 p0.3 / ach3 5 1 . s u b p / 7 . 4 p / 5 1 d a # l r w / # r w / n e l l p / 2 . 5 p # d r / 3 . 5 p v p p v s s ) e r o c ( e l a / # v d a / 0 . 5 p v 1 s s ) t r o p ( 1 l a t x 2 l a t x 1 d s / 7 . 6 p 1 c s / 6 . 6 p 0 d s / 5 . 6 p 0 c s / 4 . 6 p a3361-03 ad14 / p4.6 / pbus.14 ad13 / p4.5 / pbus.13 ad12 / p4.4 / pbus.12 ad11 / p4.3 / pbus.11 ad10 / p4.2 / pbus.10 ad9 / p4.1 / pbus.9 ad8 / p4.0 / pbus.8 ad7 / p3.7 / pbus.7 ad6 / p3.6 / pbus.6 ad5 / p3.5 / pbus.5 ad4 / p3.4 / pbus.4 ad3 / p3.3 / pbus.3 ad2 / p3.2 / pbus.2 46 45 44 43 42 41 40 39 38 37 36 35 34 xx87c196lb20 view of component as mounted on pc board 8 9 10 11 12 13 14 15 16 17 18 19 20 1 . s u b p / 1 . 3 p / 1 d a 0 . s u b p / 0 . 3 p / 0 d a # t e s e r # a e v 1 s s ) t r o p ( v c c r e v p / d x t / 0 . 2 p # e l a p / d x r / 1 . 2 p # g o r p / t n i t x e / 2 . 2 p # c n i a / 0 5 8 1 j x r / 4 . 2 p r e v p c / 0 5 8 1 j x t / 6 . 2 p # t c a p / t u o k l c / 7 . 2 p 2 h c a / 2 . 0 p 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 0 3 1 3 2 3 3 3 7 6 5 4 3 2 1 2 5 1 5 0 5 9 4 8 4 7 4 8xc196l x supplement a-6 table a-3. 83c196ld signals arranged by functional categories addr & data input/output input/output (contd) processor control name pin name pin name pin name pin ad0 22 p1.0/epa0/t2clk 44 p4.7 7 clkout 32 ad1 21 p1.1/epa1 43 p5.0 2 ea# 24 ad2 20 p1.2/epa2/t2dir 42 p5.2 6 extint 29 ad3 19 p1.3/epa3 41 p5.3 5 once# 31 ad4 18 p2.0/txd 27 p6.0/epa8 45 reset# 23 ad5 17 p2.1/rxd 28 p6.1/epa9 46 xtal1 52 ad6 16 p2.2 29 p6.4/sc0 47 xtal2 51 ad7 15 p2.4 30 p6.5/sd0 48 ad8 14 p2.6 31 p6.6/sc1 49 bus control & status ad9 13 p2.7 32 p6.7/sd1 50 name pin ad10 12 p3.0 22 adv#/ale 2 ad11 11 p3.1 21 power & ground rd# 5 ad12 10 p3.2 20 name pin wr#/wrl# 6 ad13 9 p3.3 19 v cc 26 ad14 8 p3.4 18 v cc 40 ad15 7 p3.5 17 v pp 4 p3.6 16 v ss 1 input p3.7 15 v ss 3 name pin p4.0 14 v ss 25 p0.2 33 p4.1 13 v ss 39 p0.3 34 p4.2 12 p0.4 35 p4.3 11 p0.5 36 p4.4 10 p0.6 37 p4.5 9 p0.7 38 p4.6 8 a -7 signal descriptions fig u re a-3 . 83c 1 96 l d 52 - pin p l cc pac k ag e a. 2 defa u l t c o n dition s t a b l e a - 5 l i st s t h e v a l u e s o f t h e s i g n a l s f o r t h e 8 7 c 1 9 6 l a a n d 8 7 c 19 6 l b d u r i n g v a r i o u s o p e r - ati n g co nd iti o n s . t a b le a - 6 lis t s t h e sa m e inf o r m at i o n f o r t h e 83 c 1 9 6 l d. t a ble a-4 d e f i n e s t h e sym b ols used to repr e s ent t h e pin s t atus. r efer to t h e d c c h aracterist i cs table i n the datasheet f o r act u a l s p ec i f i ca t i o ns fo r v o l , v i l , v o h , a n d v i h . t a bl e a-4. d e finit i on o f statu s sy m bol s s ymbo l de f in i t io n symb o l de f i ni t i o n 0 v oltage le s s than or e q ua l t o v o l , v i l m d 0 m ediu m pull-dow n 1 v oltage g r ea t e r than o r equal t o v o h , v i h m d 1 m ediu m pull-u p hi z high im p edanc e w k 0 w e ak p u l l -dow n loz 0 low i m pedance; s t ron g l y driv e n lo w w k 1 w e a k p u l l -u p loz 1 low i m pedance; s t ron g l y driv e n hig h od i o open-drain i / o a3403-02 p6.1 / epa9 p6.0 / epa8 p1.0 / epa0 / t2clk p1.1 / epa1 p1.2 / epa2 / t2dir p1.3 / epa3 v cc v ss p0.7 p0.6 p0.5 p0.4 p0.3 7 . 4 p / 5 1 d a # l r w / # r w / 2 . 5 p # d r / 3 . 5 p v p p v s s e l a / # v d a / 0 . 5 p v s s 1 l a t x 2 l a t x 1 d s / 7 . 6 p 1 c s / 6 . 6 p 0 d s / 5 . 6 p 0 c s / 4 . 6 p ad14 / p4.6 ad13 / p4.5 ad12 / p4.4 ad11 / p4.3 ad10 / p4.2 ad9 / p4.1 ad8 / p4.0 ad7 / p3.7 ad6 / p3.6 ad5 / p3.5 ad4 / p3.4 ad3 / p3.3 ad2 / p3.2 46 45 44 43 42 41 40 39 38 37 36 35 34 xx83c196ld view of component as mounted on pc board 8 9 10 11 12 13 14 15 16 17 18 19 20 1 . 3 p / 1 d a 0 . 3 p / 0 d a # t e s e r # a e v s s v c c d x t / 0 . 2 p d x r / 1 . 2 p t n i t x e / 2 . 2 p 4 . 2 p # e c n o / 6 . 2 p t u o k l c / 7 . 2 p 2 . 0 p 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 0 3 1 3 2 3 3 3 7 6 5 4 3 2 1 2 5 1 5 0 5 9 4 8 4 7 4 8xc196l x supplement a-8 table a-5. 87c196la, lb default signal conditions port signals alternate functions during reset# active upon reset# inactive (note 6) idle power- down p0.7:2 ach7:2 hiz hiz hiz hiz p1.0 epa0/t2clk wk0 wk0 (note 1) (note 1) p1.1 epa1 wk0 wk0 (note 1) (note 1) p1.2 epa2/t2dir wk0 wk0 (note 1) (note 1) p1.3 epa3 wk0 wk0 (note 1) (note 1) p2.0 txd wk0 wk0 (note 1) (note 1) p2.1 rxd wk0 wk0 (note 1) (note 1) p2.2 extint wk0 wk0 (note 1) (note 1) p2.4 rxj1850 (lb only) wk0 wk0 (note 1) (note 1) p2.6 once/txj1850 (lb only) md0 md0 (note 1) (note 1) p2.7 clkout clkout active, loz0/1 clkout active, loz0/1 (note 1) (note 2) p3.7:0 ad7:0 wk0 hiz (note 4) (note 4) p4.7:0 ad15:8 wk0 hiz (note 4) (note 4) p5.0 ale/adv# wk0 wk0 (note 1) (note 1) p5.2 wr#/wrl# wk0 wk0 (note 1) (note 1) p5.3 rd# wk0 wk0 (note 1) (note 1) p6.0 epa8/comp0 wk0 wk0 (note 1) (note 1) p6.1 epa9/comp1 wk0 wk0 (note 1) (note 1) p6.4 sc0 wk0 wk0 (note 1) (note 1) p6.5 sd0 wk0 wk0 (note 1) (note 1) p6.6 sc1 wk0 wk0 (note 1) (note 1) p6.7 sd1 wk0 wk0 (note 1) (note 1) ea# wk1 (note 5) wk1 wk1 wk1 reset# loz0 md1 md1 md1 v pp hiz hiz loz1 loz1 xtal1 osc input, hiz osc input, hiz osc input, hiz osc input, hiz xtal2 osc output, loz0/1 osc output, loz0/1 osc output, loz0/1 (note 3) notes: 1. if p x _mode. y = 0, port is as programmed. if p x _mode. y = 1, pin is as specified by p x _dir and the associated peripheral. 2. if p2_mode.7 = 0, pin is as programmed. if p2_mode.7 = 1, pin is loz0. 3. if xtal1 = 0, pin is loz1. if xtal1 = 1, pin is loz0. 4. if ea# = 0, port is hiz. if ea# = 1, port is open-drain i/o. 5. although ea# is weakly pulled high, do not allow it to float. always tie ea# to v cc if it is not connected to an external device. 6. the values in this column are valid until your software writes to p x _mode. a-9 signal descriptions table a-6. 83c196ld default signal conditions port signals alternate functions during reset# active upon reset# inactive (note 6) idle power- down p0.7:2 hiz hiz hiz hiz p1.0 epa0/t2clk wk1 wk1 (note 1) (note 1) p1.1 epa1 wk1 wk1 (note 1) (note 1) p1.2 epa2/t2dir wk1 wk1 (note 1) (note 1) p1.3 epa3 wk1 wk1 (note 1) (note 1) p2.0 txd wk1 wk1 (note 1) (note 1) p2.1 rxd wk1 wk1 (note 1) (note 1) p2.2 extint wk1 wk1 (note 1) (note 1) p2.4 wk1 wk1 (note 1) (note 1) p2.6 once md1 md1 (note 1) (note 1) p2.7 clkout clkout active, loz0/1 clkout active, loz0/1 (note 1) (note 2) p3.7:0 ad7:0 wk1 hiz (note 4) (note 4) p4.7:0 ad15:8 wk1 hiz (note 4) (note 4) p5.0 ale/adv# wk1 wk1 (note 1) (note 1) p5.2 wr#/wrl# wk1 wk1 (note 1) (note 1) p5.3 rd# wk1 wk1 (note 1) (note 1) p6.0 epa8 wk1 wk1 (note 1) (note 1) p6.1 epa9 wk1 wk1 (note 1) (note 1) p6.4 sc0 wk1 wk1 (note 1) (note 1) p6.5 sd0 wk1 wk1 (note 1) (note 1) p6.6 sc1 wk1 wk1 (note 1) (note 1) p6.7 sd1 wk1 wk1 (note 1) (note 1) ea# wk1 (note 5) wk1 wk1 wk1 reset# loz0 md1 md1 md1 v pp hiz hiz loz1 loz1 xtal1 osc input, hiz osc input, hiz osc input, hiz osc input, hiz xtal2 osc output, loz0/1 osc output, loz0/1 osc output, loz0/1 (note 3) notes: 1. if p x _mode. y = 0, port is as programmed. if p x _mode. y = 1, pin is as specified by p x _dir and the associated peripheral. 2. if p2_mode.7 = 0, pin is as programmed. if p2_mode.7 = 1, pin is loz0. 3. if xtal1 = 0, pin is loz1. if xtal1 = 1, pin is loz0. 4. if ea# = 0, port is hiz. if ea# = 1, port is open-drain i/o. 5. although ea# is weakly pulled high, do not allow it to float. always tie ea# to v cc if it is not connected to an external device. 6. the values in this column are valid until your software writes to p x _mode. glossary glossary-1 glossary this glossary defines acronyms, abbreviations, and terms that have special meaning in this man- ual. (chapter 1 discusses notational conventions and general terminology.) absolute error the maximum difference between corresponding actual and ideal code transitions . absolute error accounts for all deviations of an actual a/d converter from an ideal converter. accumulator a register or storage location that forms the result of an arithmetic or logical operation. actual characteristic a graph of output code versus input voltage of an actual a/d converter . an actual characteristic may vary with temperature, supply voltage, and frequency conditions. a/d converter analog-to-digital converter. an internal peripheral that converts an analog input to a digital value. alu arithmetic-logic unit. the part of the ralu that processes arithmetic and logical operations. assert the act of making a signal active (enabled). the polarity (high or low) is defined by the signal name. active-low signals are designated by a pound symbol (#) suffix; active-high signals have no suffix. to assert rd# is to drive it low; to assert ale is to drive it high. attenuation a decrease in amplitude; voltage decay. bit a binary digit. bit a single-bit operand that can take on the boolean values, true and false. bit arbitration the process of settling conflicts that occur when multiple nodes attempt to transmit a bit or symbol across a single bus at the same time. break-before-make the property of a multiplexer which guarantees that a previously selected channel is deselected before a new channel is selected. (that is, break-before-make ensures that the a/d converter will not short inputs together.) 8xc196l x supplement glossary-2 byte any 8-bit unit of data. byte an unsigned, 8-bit variable with values from 0 through 2 8 C1. ccbs chip configuration bytes. the chip configuration registers ( ccrs ) are loaded with the contents of the ccbs after a reset. ccrs chip configuration registers. registers that define the environment in which the microcontroller will be operating. the chip configuration registers are loaded with the contents of the ccbs after a reset. channel-to-channel matching error the difference between corresponding code transitions of actual characteristics taken from different a/d converter channels under the same temperature, voltage, and frequency conditions. this error is caused by differences in dc input leakage and on-channel resistance from one multiplexer channel to another. characteristic a graph of output code versus input voltage; the transfer function of an a/d converter . chip-select unit the integrated module that selects an external memory device during an external bus cycle. clear the 0 value of a bit or the act of giving it a 0 value. see also set . code 1) a set of instructions that perform a specific function; a program. 2) the digital value output by the a/d converter . code center the voltage corresponding to the midpoint between two adjacent code transitions on the a/d converter . code transition the point at which the a/d converter s output code changes from q to q+1. the input voltage corre- sponding to a code transition is defined as the voltage that is equally likely to produce either of two adjacent codes. code width the voltage change corresponding to the difference between two adjacent code transitions . code width deviations cause differential nonlinearity and nonlin- earity errors. glossary-3 glossary contention the detection of conflicting symbols or bits on the bus. crosstalk see off-isolation. dc input leakage leakage current from an analog input pin to ground or to the reference voltage (v ref ). deassert the act of making a signal inactive (disabled). the polarity (high or low) is defined by the signal name. active-low signals are designated by a pound symbol (#) suffix; active-high signals have no suffix. to deassert rd# is to drive it high; to deassert ale is to drive it low. demultiplexed bus the configuration in which the microcontroller uses separate lines for address and data (address on a20:0; data on ad15:0 for a 16-bit bus or ad7:0 for an 8-bit bus). see also multiplexed bus . differential nonlinearity the difference between the actual code width and the ideal one-lsb code width of the terminal-based characteristic of an a/d converter. it provides a measure of how much the input voltage may have changed in order to produce a one-count change in the conversion result. differential nonlinearity is a measure of local code-width error; nonlinearity is a measure of overall code-transition error. doping the process of introducing a periodic table group iii or group v element into a group iv element (e.g., silicon). a group iii impurity (e.g., indium or gallium) results in a p-type material . a group v impurity (e.g., arsenic or antimony) results in an n- type material . double-word any 32-bit unit of data. double-word an unsigned, 32-bit variable with values from 0 through 2 32 C1. epa event processor array. an integrated peripheral that provides high-speed input/output capability. esd electrostatic discharge. 8xc196l x supplement glossary-4 external address a 21 -bit address is presented on the microcontrollers pins. the address decoded by an external device depends on how many of these address pins the external system uses. see also internal address . f lowercase f represents the frequency of the internal clock. far constants constants that can be accessed only with extended instructions. see also near constants . far data data that can be accessed only with extended instruc- tions. see also near data . feedthrough the attenuation from an input voltage on the selected channel to the a/d output after the sample window closes. the ability of the a/d converter to reject an input on its selected channel after the sample window closes. fet field-effect transistor. full-scale error the difference between the ideal and actual input voltage corresponding to the final (full-scale) code transition of an a/d converter . hold latency the time it takes the microcontroller to assert hlda# after an external device asserts hold#. ideal characteristic the characteristic of an ideal a/d converter . an ideal characteristic is unique: its first code transition occurs when the input voltage is 0.5 lsb, its full-scale (final) code transition occurs when the input voltage is 1.5 lsb less than the full-scale reference, and its code widths are all exactly 1.0 lsb. these properties result in a conversion without zero-offset , full-scale , or linearity errors. quantizing error is the only error seen in an ideal a/d converter. input leakage current leakage from an input pin to power or ground. input series resistance the effective series resistance from an analog input pin to the sample capacitor of an a/d converter . integer any member of the set consisting of the positive and negative whole numbers and zero. integer a 16-bit, signed variable with values from C2 15 through +2 15 C1. glossary-5 glossary internal address the 24-bit address that the microcontroller generates. see also external address . interrupt controller the module responsible for handling interrupts that are to be serviced by interrupt service routines that you provide. also called the programmable interrupt controller (pic) . interrupt latency the total delay between the time that an interrupt is generated (not acknowledged) and the time that the microcontroller begins executing the interrupt service routine or pts routine . determine the instruction in your code that has the longest execution time and use that execution time in calculating interrupt latency. interrupt service routine a software routine that you provide to service a standard interrupt request. interrupt vector a location in special-purpose memory that holds the starting address of an interrupt service routine . j1850 an integrated communications controller peripheral that supports the 10.4 kb/s variable pulse-width (vpw) medium-speed, class b, in-vehicle network protocol. isr see interrupt service routine. linearity errors see differential nonlinearity and nonlinearity . long-integer a 32-bit, signed variable with values from C2 31 through +2 31 C1. lsb 1) least-significant bit of a byte or least-significant byte of a word. 2) in an a/d converter, the reference voltage divided by 2 n , where n is the number of bits to be converted. for a 10-bit converter with a reference voltage of 5.12 volts, one lsb is equal to 5.0 millivolts (5.12 ? 2 10 ). lsw least-significant word of a double-word or quad- word. 8xc196l x supplement glossary-6 maskable interrupts all interrupts except stack overflow, unimplemented opcode, and software trap. maskable interrupts can be disabled (masked) by the individual mask bits in the interrupt mask registers, and their servicing can be disabled by the di (disable interrupt service) instruction. each maskable interrupt can be assigned to the pts for processing. monotonic the property of successive approximation converters which guarantees that increasing input voltages produce adjacent codes of increasing value, and that decreasing input voltages produce adjacent codes of decreasing value. (in other words, a converter is monotonic if every code change represents an input voltage change in the same direction.) large differ- ential nonlinearity errors can cause the converter to exhibit nonmonotonic behavior. msb most-significant bit of a byte or most-significant byte of a word . msw most-significant word of a double-word or quad- word. multiplexed bus the configuration in which the microcontroller uses both a20:0 and ad15:0 for address and also uses ad15:0 for data. see also demultiplexed bus . n -channel fet a field-effect transistor with an n -type conducting path (channel). n -type material semiconductor material with introduced impurities ( doping ) causing it to have an excess of negatively charged carriers. near constants constants that can be accessed with nonextended instructions. constants in page 00h are near constants. see also far constants . near data data that can be accessed with nonextended instruc- tions. data in page 00h is near data. see also far data . no missing codes an a/d converter has no missing codes if, for every output code, there is a unique input voltage range which produces that code only. large differential nonlinearity errors can cause the converter to miss codes. glossary-7 glossary nonlinearity the maximum deviation of code transitions of the terminal-based characteristic from the corre- sponding code transitions of the ideal characteristic . nonmaskable interrupts interrupts that cannot be masked (disabled) and cannot be assigned to the pts for processing. the nonmaskable interrupts are stack overflow, unimple- mented opcode, software trap, and nmi. the di (disable interrupt service) and ei (enable interrupt service) instructions have no effect on nonmaskable interrupts. npn transistor a transistor consisting of one part p-type material and two parts n-type material . off-isolation the ability of an a/d converter to reject (isolate) the signal on a deselected (off) output. p -channel fet a field-effect transistor with a p -type conducting path. p -type material semiconductor material with introduced impurities ( doping ) causing it to have an excess of positively charged carriers. pc program counter. phase-locked loop a component of the clock generation circuitry. the phase-locked loop (pll) and the input pin (pllen) combine to enable the microcontroller to attain its maximum operating frequency with an external clock whose frequency is either equal to or one-half that maximum frequency or with an external oscillator whose frequency is one-half that maximum frequency. pic programmable interrupt controller. the module responsible for handling interrupts that are to be serviced by interrupt service routines that you provide. also called simply the interrupt controller . pih peripheral interrupt handler. an integrated module that provides interrupt vectors for specific epa interrupt requests to the interrupt controller or pts . pll see phase-locked loop . 8xc196l x supplement glossary-8 prioritized interrupt nmi, stack overflow, or any maskable interrupt . two of the nonmaskable interrupts (unimplemented opcode and software trap) are not prioritized; they vector directly to the interrupt service routine when executed. program memory a partition of memory where instructions can be stored for fetching and execution. protected instruction an instruction that prevents an interrupt from being acknowledged until after the next instruction executes. the protected instructions are di, ei, dpts, epts, popa, popf, pusha, and pushf. psw processor status word. the high byte of the psw is the status byte, which contains one bit that globally enables or disables servicing of all maskable interrupts, one bit that enables or disables the pts , and six boolean flags that reflect the state of the current program. the low byte of the psw is the int_mask register. a pusha or popa instruction saves or restores both bytes (psw + int_mask); a pushf or popf saves or restores only the psw. pts peripheral transaction server. the microcoded hardware interrupt processor. ptscb see pts control block . pts control block a block of data required for each pts interrupt . the microcode executes the proper pts routine based on the contents of the pts control block. pts cycle the microcoded response to a single pts interrupt request. pts interrupt any maskable interrupt that is assigned to the pts for interrupt processing. pts mode a microcoded response that enables the pts to complete a specific task quickly. pts routine the entire microcoded response to multiple pts interrupt requests. the pts routine is controlled by the contents of the pts control block . pts transfer the movement of a single byte or word from the source memory location to the destination memory location. glossary-9 glossary pts vector a location in special-purpose memory that holds the starting address of a pts control block . quad-word an unsigned, 64-bit variable with values from 0 through 2 64 C1. the quad-word variable is supported only as the operand for the ebmovi instruction. quantizing error an unavoidable a/d conversion error that results simply from the conversion of a continuous voltage to its integer digital representation. quantizing error is always 0.5 lsb and is the only error present in an ideal a/d converter . ralu register arithmetic-logic unit. a part of the cpu that consists of the alu , the psw , the master pc , the microcode engine, a loop counter, and six registers. repeatability error the variation in code transitions when comparing a number of actual characteristics from the same converter on the same channel with the same temper- ature, voltage, and frequency conditions. the amount of repeatability error depends on the comparators ability to resolve very similar voltages and the extent to which random noise contributes to the error. reserved memory a memory location that is reserved for factory use or for future expansion. do not use a reserved memory location except to initialize it. resolution the number of input voltage levels that an a/d converter can unambiguously distinguish between. the number of useful bits of information that the converter can return. sample capacitor a small (2C3 pf) capacitor used in the a/d converter circuitry to store the input voltage on the selected input channel. sample delay the time period between the time that a/d converter receives the start conversion signal and the time that the sample capacitor is connected to the selected channel. sample delay uncertainty the variation in the sample delay . sample time the period of time that the sample window is open. (that is, the length of time that the input channel is actually connected to the sample capacitor .) 8xc196l x supplement glossary-10 sample time uncertainty the variation in the sample time . sample window the period of time that begins when the sample capacitor is attached to a selected channel of an a/d converter and ends when the sample capacitor is disconnected from the selected channel. sampled inputs all input pins, with the exception of reset#, are sampled inputs. the input pin is sampled one state time before the read buffer is enabled. sampling occurs during ph1 (while clkout is low) and resolves the value (high or low) of the pin before it is presented to the internal bus. if the pin value changes during the sample time, the new value may or may not be recorded during the read. reset# is a level-sensitive input. extint is normally a sampled input; however, the powerdown circuitry uses extint as a level-sensitive input during powerdown mode. sar successive approximation register. a component of the a/d converter . set the 1 value of a bit or the act of giving it a 1 value. see also clear . sfr special-function register. short-integer an 8-bit, signed variable with values from C2 7 through +2 7 C1. sign extension a method for converting data to a larger format by filling the upper bit positions with the value of the sign. this conversion preserves the positive or negative value of signed integers. sink current current flowing into a device to ground. always a positive value. source current current flowing out of a device from v cc . always a negative value. sp stack pointer. special interrupt any of the three nonmaskable interrupts (unimple- mented opcode, software trap, or nmi). glossary-11 glossary special-purpose memory a partition of memory used for storing the interrupt vectors , pts vectors , chip configuration bytes, and several reserved locations. standard interrupt any maskable interrupt that is assigned to the interrupt controller for processing by an interrupt service routine . state time (or state) the basic time unit of the microcontroller; the combined period of the two internal timing signals, ph1 and ph2. because the microcontroller can operate at many frequencies, this manual defines time requirements in terms of state times rather than in specific units of time. successive approximation an a/d conversion method that uses a binary search to arrive at the best digital representation of an analog input. t lowercase t represents the period of the internal clock. temperature coefficient change in the stated variable for each degree centigrade of temperature change. temperature drift the change in a specification due to a change in temperature. temperature drift can be calculated by using the temperature coefficient for the specification. terminal-based characteristic an actual characteristic that has been translated and scaled to remove zero-offset error and full-scale error . a terminal-based characteristic resembles an actual characteristic with zero-offset error and full- scale error removed. transfer function a graph of output code versus input voltage; the characteristic of the a/d converter . transfer function errors errors inherent in an analog-to-digital conversion process: quantizing error , zero-offset error , full-scale error , differential nonlinearity , and nonlinearity . errors that are hardware-dependent, rather than being inherent in the process itself, include feedthrough , repeatability , channel-to-channel matching , off- isolation , and v cc rejection errors. uart universal asynchronous receiver and transmitter. a part of the serial i/o port. 8xc196l x supplement glossary-12 v cc rejection the property of an a/d converter that causes it to ignore (reject) changes in v cc so that the actual characteristic is unaffected by those changes. the effectiveness of v cc rejection is measured by the ratio of the change in v cc to the change in the actual characteristic . vpw variable pulse-width. a forced high/low symbol transition formatting scheme that tracks the duration between two consecutive transitions and the level of the bus, active or passive. wait state time spent waiting for an operation to take place. wait states are added to external bus cycles to allow a slow memory device to respond to a request from the microcontroller. watchdog timer an internal timer that resets the microcontroller if software fails to respond before the timer overflows. wdt watchdog timer . an internal timer that resets the microcontroller if software fails to respond before the timer overflows. word any 16-bit unit of data. word an unsigned, 16-bit variable with values from 0 through 2 16 C1. zero extension a method for converting data to a larger format by filling the upper bit positions with zeros. zero-offset error an ideal a/d converter s first code transition occurs when the input voltage is 0.5 lsb. zero-offset error is the difference between 0.5 lsb and the actual input voltage that triggers an a/d converters first code transition. index index-1 index a address map, 3-1 address partitions map, 3-1 otprom, 11-1 program memory, 11-1 special-purpose memory, 11-1 ale, idle, powerdown, reset status, a-8, a-9 b block diagram 8xc196l x , 2-2 c clkout and internal timing, 2-2C2-4 idle, powerdown, reset status, a-8, a-9 output frequency, 2-5 reset status, 5-2 clock circuitry, 2-3, 10-2 d delay register, 8-20 design considerations, 9-2 device pin reset status, a-8, a-9 documents, related, 1-2 e ea#, idle, powerdown, reset status, a-8, a-9 epa interrupt mask 1 register, 7-4 interrupt mask register, 7-4 interrupt pending 1 register, 7-5 interrupt pending register, 7-5 interrupt priority vector register, 7-6 esd protection, 5-2, 5-5 f formulas clock period (t), 2-4 ph1 and ph2 frequency, 2-4 state time, 2-4 frequency (f), 2-4 f xtal 1 , 2-4 h hardware, pin reset status, a-8, a-9 i idle mode pin status, a-8, a-9 internal timing, 2-2, 10-1 interrupts mask 1 register, 4-4 mask register, 4-3 pending 1 register, 4-6 pending register, 4-5 priorities, 4-2 sources, 4-2 vectors, 4-2 j j1850 communications controller, 8-3C8-21 delay compensation, 8-20 in-frame response command register, 8-17 interrupt status register, 8-21 oscillator prescaler configuration register, 8-18 receiver register, 8-15 registers, 8-3C8-4 signals, 8-3 transmitter register, 8-14 m manual contents, summary, 1-1C1-2 n noise, reducing, 5-2 o once mode, entering and exiting, 10-2 otprom address map, 11-1 index-2 p period (t), 2-4 port 0 idle, powerdown, reset status, a-8, a-9 overview, 5-1 port 1 configuring, 5-3 idle, powerdown, reset status, a-8, a-9 overview, 5-1 port 2 configuring, 5-3 idle, powerdown, reset status, a-8, a-9 overview, 5-1 p2.7 reset status, 5-2 port 3 idle, powerdown, reset status, a-8, a-9 internal structure, 5-5 overview, 5-1 port 4 idle, powerdown, reset status, a-8, a-9 internal structure, 5-5 overview, 5-1 port 5 configuring, 5-3 idle, powerdown, reset status, a-8, a-9 overview, 5-1 port 6 configuring, 5-3 idle, powerdown, reset status, a-8, a-9 overview, 5-1 ports, input buffers, 5-2 powerdown mode, pin status, a-8, a-9 pts select register, 4-7 pts service register, 4-8 r rd#, idle, powerdown, reset status, a-8, a-9 register file and windowing, 3-2 description, 3-3 registers epa_mask, 7-4 epa_mask1, 7-4 epa_pend, 7-5 epa_pend1, 7-5 epaipv, 7-6 int_mask, 4-3 int_mask1, 4-4 int_pend, 4-5 int_pend1, 4-6 j_cfg, 8-18 j_cmd, 8-17 j_dly, 8-20 j_rx, 8-15 j_stat, 8-21 j_tx, 8-14 ptssel, 4-7 ptssrv, 4-8 rstsrc, 9-1 ssio0_clk, 6-1 ssio1_clk, 6-2 usfr1, 2-6 reset pin status, a-8, a-9 status of clkout/p2.7, 5-2 reset source indicator register, 9-1 reset#, idle, powerdown, reset status, a-8, a-9 s serial port programming mode, 11-5 signals default conditions, a-8, a-9 status symbols defined, a-7 state time, defined, 2-4 symbols, signal status, a-7 synchronous serial port 0 clock register, 6-1 synchronous serial port 1 clock register, 6-2 u unerasable prom 1 register, 2-6 w windows and address-mapped sfrs, 3-6 locations that cannot be windowed, 3-6 wsr values and direct addresses, 3-6 wr#, idle, powerdown, reset status, a-8, a-9 |
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